دانلود کتاب Transactions on High-Performance Embedded Architectures and Compilers IV

فهرست مطالب :

Front Matter....Pages -
A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors....Pages 1-20
Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces....Pages 21-41
Compiler Directed Issue Queue Energy Reduction....Pages 42-62
A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors....Pages 63-83
Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors....Pages 84-110
A Highly Scalable Parallel Implementation of H.264....Pages 111-134
Communication Based Proactive Link Power Management....Pages 135-154
Finding Extreme Behaviors in Microprocessor Workloads....Pages 155-174
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture....Pages 175-194
Transaction Reordering to Reduce Aborts in Software Transactional Memory....Pages 195-214
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture....Pages 215-233
A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM....Pages 234-253
Software Transactional Memory Validation – Time and Space Considerations....Pages 254-273
Tiled Multi-Core Stream Architecture....Pages 274-293
An Efficient and Flexible Task Management for Many Cores....Pages 294-310
On Two-Layer Brain-Inspired Hierarchical Topologies – A Rent’s Rule Approach –....Pages 311-333
Advanced Packet Segmentation and Buffering Algorithms in Network Processors....Pages 334-353
Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation....Pages 354-369
A Cost Model for Partial Dynamic Reconfiguration....Pages 370-390
Heterogeneous Design in Functional DIF....Pages 391-408
Signature-Based Calibration of Analytical Performance Models for System-Level Design Space Exploration....Pages 409-425
Back Matter....Pages -