دانلود کتاب Analog and Mixed-Signal Circuits in Nanoscale CMOS

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Foreword Acknowledgment Introduction Contents Part I: Radio Front-Ends and Clock References High-Performance SAW-Less TDD/FDD RF Front-Ends 1 Introduction 2 SAW-Less Multiband Transceiver Using an N-Path SC Gain Loop 2.1 Principle of the SC Gain Loop as a TXR 2.2 N-Path SC Gain Loop as a TX TX-Mode Architecture Functional View of the TX Mode TX-Mode Open-Loop Equivalent Model Gain Response Noise Analysis OB Noise, Passband Roll-off, and Harmonic Emission Other Implementation Details 2.3 N-Path SC Gain Loop as a RX 2.4 Four-Phase LO Generator and TX-/RX-Mode Logics 2.5 Measurement Results TX Mode RX Mode 2.6 Conclusions 3 1.4-2.7-GHz FDD SAW-Less Transmitter for 5G-NR Using an N-Path Filter Modulator 3.1 Existing FIL-MOD and Proposed BW-Ext FIL-MOD Existing FIL-MOD The Proposed BW-Ext FIL-MOD 3.2 TX Design and Analysis Architecture Functional View of the TX LTI Model of the BW-Ext FIL-MOD Isolated BB Input Network Wideband TIA-Based PAD Four-Phase 25%-Duty-Cycle LOGEN Other Implementation Details 3.3 Measurement Results 3.4 Conclusions References Power-Efficient RF and mm-Wave VCOs/PLL 1 Introduction 2 Inverse Class-F (Class-F-1) VCO 2.1 Toward the Power-Efficient Low-Phase-Noise Oscillators 2.2 Principle of the Class-F-1 Oscillator 2.3 A 3.5-4.5 GHz Low-Phase-Noise Class-F-1 VCO 3 Wideband Mode-Switching MM-Wave VCO 3.1 Capacitive and Resonant Mode-Switching Techniques 3.2 Inductive Mode-Switching Technique 3.3 A 42.9-50.6 GHz Quad-Core-Coupled VCO Using Inductive Mode-Switching Technique 4 Multi-Resonant-RLCM-Tank VCO 5 Isolated Subsampling PLL References Ultra-Low-Voltage Clock References 1 Introduction 2 Regulation-Free Sub-0.5 V 16/24 MHz Crystal Oscillator for Energy-Harvesting BLE 2.1 Motivation 2.2 Fast Startup XO Using Dual-Mode gm Scheme and SSCI Scalable Self-Reference Chirp Injection (SSCI) Dual-Mode gm Scheme 2.3 Transistor-Level Implementation 2.4 Experimental Results and Comparison with State of the Art 3 A 0.35 V 5200 μm2 2.1 MHz Temperature-Resilient Relaxation Oscillator with 667 fJ/cycle Energy Efficiency Using an Asymmetri... 3.1 Motivation 3.2 Asymmetric Swing-Boosted RC Network 3.3 Circuit Implementation ULV Comparator with Dual-Path Amplifiers Delay Generators CLK Boosters 3.4 Measurement Results 4 Conclusions References Part II: Data Converters Low-Power Nyquist ADCs 1 Introduction 2 12b 1 GS/s Three-Stage Pipeline-SAR ADC 2.1 Residue Amplifier (RA) Discussion Incomplete-Settled RA Complete-Settled RA Proposed Gm-R-based RA Two-Stage RA Consideration 2.2 ADC Implementation 2.3 Measurement Results 3 0.6 V PVT-Robust 13b 20 MS/s SAR-TDC ADC 3.1 Voltage-Time Hybrid ADC Architecture 3.2 Stage Bit Number Arrangement 3.3 PVT Inner Tracking Technique Incomplete-Settled RA Discharging-Based VTC PVT Tracking Implementation 3.4 Measurement Results 4 6b 3.3 GS/s Pipeline ADC 4.1 Post-amplification Residue Generation 4.2 Linearized Dynamic Amplifier 4.3 On-Chip Calibration 4.4 Overall ADC Implementation 4.5 Measurement Results 5 8b 10 GS/s Time-Domain ADC 5.1 Time-Interleaved Architecture Considerations 5.2 Sub- time-Domain ADC Architecture 5.3 16x Time Interpolation-Based TDC 5.4 Low Metastability Time Residue Logic 5.5 Measurement Results References High-Performance Oversampling ADCs 1 Introduction 2 Sturdy Multistage Noise-Shaping (MASH) Continuous-Time (CT)-Delta-Sigma Modulator (DSM) 2.1 Related Prior Arts 2.2 Proposed CT Sturdy MASH with DAC Nonlinearity Tolerance 2.3 Experimental Results 3 A 100 MHz Bandwidth Continuous-Time Sigma-Delta Modulator with Preliminary Sampling and Quantization 3.1 Preliminary Sampling and Quantization (PSQ) 3.2 Measurement Results 4 A 40 MHz Bandwidth Noise-Shaping Pipeline SAR ADC with 0-N MASH Structure 4.1 SAR-Assisted NS Pipeline ADC 4.2 Measurement Results 5 A 25 MHz Bandwidth Gain Error-Tolerant N-0 MASH Noise-Shaping Pipeline SAR ADC 5.1 Measurement Results References Part III: Energy Harvesters and Power Converters Integrated Energy Harvesting Interfaces 1 Introduction 2 Flipping Capacitor Rectifier for Vibration Energy Harvesting 2.1 Conventional PEH Interfaces 3 Reconfigurable SC DC-DC Boost Converter for Solar/Thermal Energy Harvesting 3.1 SC Converter Power Stage Losses 3.2 Two-Dimensional Series-Parallel (SP)-Based Topology for Fractional VCR Generation 3.3 Algebraic Series-Parallel (ASP)-Based SC Topology Development 3.4 ASP Topology Generation and Analysis 3.5 ASP-Based SC Boost Converter Implementation 4 Conclusions References Fully Integrated Switched-Capacitor Power Converters 1 Introduction 2 Topology Generation 2.1 Efficiency and Power Density Trade-Off 2.2 Two-Phase Limitation and Three-Phase Operation 2.3 Review of Other Topologies 3 Efficiency Optimization 3.1 Unified Models for Losses in the SC Converter 3.2 Switching and Parasitic Losses 3.3 Gate Switching Loss and Parasitic Loss Reduction 3.4 Efficiency Optimization 4 Clock Generation and Distribution: 123-Phase Converter Ring 4.1 General Concept of Multiphase Interleaving 4.2 Clock Generation: Centralized Versus Distributive 4.3 123-Phase SC Converter Ring 5 Multi-Output Switched-Capacitor Converter 6 Conclusions References Hybrid Architectures and Controllers for Low-Dropout Regulators 1 Introduction 2 Control Method and Power Stage Selection 2.1 Power Stage Comparison 2.2 LDO Controller 3 Analog-Digital Hybrid LDO 3.1 Analog-Assisted Digital LDOs 3.2 An Analog-Proportional Digital Integral Multiloop Digital LDO 3.3 A 1.2A Calibration-Free Hybrid LDO with in-Loop Quantization 4 Multiphase Switching LDO 4.1 Ripple Analysis 4.2 RAMP-Based PWM Control 4.3 Four-Phase PWM Control 4.4 Current Balancing 4.5 Dual-Loop Four-Phase PWM Control Switching LDO 5 Conclusions References Index