دانلود کتاب ANALOG-TO-DIGITAL CONVERSION

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Preface to the Fourth Edition Preface to the Third Edition Preface to the Second Edition Preface to the First Edition Acknowledgments Contents About the Author List of Symbols Reference Tables and Figures 1 Introduction References 2 Mathematics 2.1 Algebra and Trigonometry 2.1.1 Derivatives and Integrals 2.1.2 Taylor series 2.1.3 Fourier Transform 2.1.4 Fourier Series 2.1.5 Linearity and Distortion 2.1.6 Laplace Transform 2.1.7 z-Transform 2.2 Statistics 2.2.1 Basic Statistical Operations 2.2.2 Poisson and Gauss Distributions 2.2.3 Practical Estimation 2.2.4 Correlation 2.2.5 Functions of Statistical Variables Exercises References 3 Electrical Theory 3.1 Resistivity 3.1.1 Power and Temperature 3.1.2 Voltage and Temperature Coefficient 3.1.3 Measuring Resistance 3.1.4 Electromigration 3.1.5 Thermal Noise 3.1.6 1/f Noise 3.1.7 Shot Noise 3.2 Maxwell Equations 3.2.1 Inductors 3.2.2 Energy in a Coil 3.2.3 Straight-Wire Inductance 3.2.4 Skin Effect and Eddy Current 3.2.5 Transformer 3.2.6 Capacitors 3.2.7 Energy in a Capacitor 3.2.8 Coaxial Cable 3.3 Network Theory 3.3.1 Kirchhoff's Laws, Thevenin, Norton, and Superposition 3.3.2 Energy and Power 3.3.3 Digital Power Consumption and Partial Charging 3.3.4 Two-Port Networks 3.3.5 Feedback 3.3.6 Bode Plot 3.3.7 Time Constant and Bandwidth 3.3.8 Filters 3.3.9 RLC Filters 3.3.10 Sallen–Key and gm-C Filters 3.3.11 Gyrator Exercises References 4 Semiconductors 4.1 Semiconductor Materials 4.1.1 Bandgap and Boltzmann 4.1.2 Semiconductor Resistivity 4.1.3 Mott–Gurney Law 4.1.4 Temperature and Voltage Coefficients 4.1.5 Matching of Resistors 4.2 PN-Junction 4.2.1 Current in a Diode 4.2.2 Temperature Behavior 4.2.3 Linearization of Diodes 4.2.4 Diode-Based Circuits 4.3 Bipolar Junction Transistor 4.3.1 Concentrations in a Bipolar Transistor 4.3.2 Bipolar Circuits 4.3.3 Darlington Pair 4.4 MOS Capacitor 4.4.1 Gate Capacitance 4.4.2 Capacitors Between Layers 4.4.3 Voltage and Temperature Coefficient 4.4.4 Matching of Capacitors 4.5 The MOS Transistor 4.5.1 Different Operating Regimes 4.5.2 MOS Transistor Current 4.5.3 Threshold Voltage 4.5.4 Weak-Inversion Current 4.5.5 Large Signal and Small Signal 4.5.6 Drain Voltage Modulation 4.5.7 Output Impedance 4.5.8 Matching of MOS Transistors 4.5.9 High-Frequency Behavior 4.5.10 Leakage 4.5.11 Temperature Coefficient 4.5.12 Noise in MOS Transistors 4.5.13 Noise Cancellation 4.5.14 Latch-up 4.5.15 Enhancement and Depletion Transistors 4.5.16 Advanced Device Architectures 4.5.17 MOS Models Exercises References 5 Electronic Circuits 5.1 Basic Circuits 5.1.1 Classification of Amplifiers 5.1.2 One-Transistor Amplifier 5.1.3 Inverter and Latch 5.1.4 Source Follower 5.1.5 Differential Pair 5.1.6 Differential Difference Pair 5.1.7 Degeneration 5.1.8 Mixers and Variable Gain Amplifiers 5.1.9 Current Mirror 5.1.10 Cascode Variants 5.1.11 Gain Boosting 5.2 Operational Amplifiers 5.2.1 Single-Stage Amplifier 5.2.2 Folded Cascode Amplifier 5.2.3 Miller Operational Amplifier 5.2.4 Choosing the W/L Ratios in a Miller Opamp 5.2.5 Dominant Pole Amplifier 5.2.6 Feedback in Electronic Circuits 5.2.7 Biasing Circuits 5.2.8 Opamps and OTAs 5.2.9 Switched-Capacitor Circuits 5.2.10 Differential Design 5.3 Oscillators 5.3.1 LC Oscillators 5.3.2 Quartz Oscillators 5.3.3 RC Oscillators 5.3.4 Phase-Locked Loop 5.3.5 Oscillators: Phase Noise 5.3.6 Jitter Exercises References 6 Accuracy: Deterministic and Random Errors 6.1 Design by Ratio 6.2 Variability 6.3 Deterministic Electrical Offsets 6.3.1 Equal Dimensions 6.3.2 Offset Caused by Electrical Differences 6.3.3 Capacitors 6.3.4 Resistors 6.3.5 Linear Gradient 6.3.6 Temperature Gradients 6.4 Technology and Accuracy 6.4.1 Lithography 6.4.2 Proximity Effects 6.4.3 Implantation Effects 6.4.4 Offset Caused by Stress 6.4.5 Issues with Wiring 6.4.6 Offset Mitigation 6.5 Random Matching 6.5.1 Random Fluctuations in Devices 6.5.2 Poisson and Gauss 6.5.3 MOS Threshold Mismatch 6.5.4 Current Factor Mismatch 6.5.5 Current Mismatch in Strong and Weak Inversion 6.5.6 Mismatch for Various Processes 6.5.7 Application to Other Components 6.5.8 Advanced Device Architectures 6.5.9 Modeling Remarks 6.6 Design Consequences 6.6.1 Analog Design 6.6.2 Digital Design 6.6.3 Drift 6.6.4 Limits of Power and Accuracy Exercises References 7 Sampling 7.1 Sampling in Time and Frequency 7.1.1 Dirac Sequence 7.1.2 Sampling Signals 7.1.3 Sampling Limit: Nyquist Criterion 7.2 Sampling Aspects 7.2.1 Down-Sampling 7.2.2 Subsampling and Decimation 7.2.3 Alias Filter 7.2.4 Alias Removal After Digital-to-AnalogConversion 7.2.5 Getting Around Nyquist? 7.2.6 Fourier Uncertainty 7.3 Modulation and Chopping 7.3.1 Modulation 7.3.2 Chopping 7.4 Reconstruction of Sampled Data 7.5 Noise 7.5.1 Sampled Noise 7.5.2 Differential Noise 7.6 Jitter 7.6.1 Jitter of the Sampling Pulse 7.6.2 Driving a Sampling Pulse 7.6.3 Optical Sampling 7.7 Time-Discrete Filtering 7.7.1 Finite Impulse Response Filters 7.7.2 Half-Band Filters 7.7.3 IIR Filters Exercises References 8 Sample-and-Hold Circuits 8.1 Track-and-Hold and Sample-and-Hold Circuits 8.2 Artifacts in T&H Circuits 8.2.1 Pedestal Step 8.2.2 Droop 8.2.3 Hold-Mode Feed-Through 8.3 Capacitor and Switch Implementations 8.3.1 Capacitor 8.3.2 Switch Impedance 8.3.3 Complementary Switch 8.3.4 High Voltages 8.3.5 Bootstrap Techniques 8.3.6 Threshold Modulation 8.3.7 Bottom-Plate Sampling 8.4 T&H Circuit Topologies 8.4.1 Driving a T&H Configuration 8.4.2 Buffering the Hold Capacitor 8.4.3 Switched-Capacitor T&H Circuits 8.4.4 Flip-Around T&H Circuit 8.4.5 Offset and Noise in Flip-Around Circuits 8.4.6 Differential Flip-Around Architecture 8.4.7 MDAC: Amplifying T&H Circuit 8.4.8 T&H with a Level-Shifting Opamp 8.4.9 Correlated Double Sampling 8.4.10 Bipolar T&H Circuit 8.4.11 Distortion and Noise Exercises References 9 Quantization 9.1 Resolution 9.2 Quantization Error 9.2.1 1-Bit Quantization 9.2.2 2-6 Bit Quantization 9.2.3 7-Bit and Higher Quantization 9.3 Signal-to-Quantization Error Ratio 9.3.1 SNQR Definition 9.3.2 Related Definitions 9.3.3 Nyquist Rate and Oversampled Architectures 9.4 Linearity 9.4.1 Integral Non-Linearity (INL) 9.4.2 Differential Non-Linearity (DNL) 9.5 Modeling INL and DNL 9.5.1 From INL to Distortion 9.5.2 DNL and Quantization 9.5.3 Non-uniform Quantization 9.5.4 Dither 9.6 Figure-of-Merit 9.6.1 Figure-of-Merit: Schreier 9.6.2 Figure-of-Merit: Walden 9.6.3 Figure-of-Merit: Digital-to-Analog Converters 9.6.4 Figure-of-Merit: Risks Exercises References 10 Reference Circuits 10.1 General Requirements 10.2 Bandgap Voltage Reference Circuits 10.2.1 Principle 10.2.2 Bipolar Devices in CMOS 10.2.3 Standard CMOS Bandgap Circuit 10.2.4 Artifacts: Start-Up 10.2.5 Artifacts: Bandwidth 10.2.6 Artifacts: Mismatch and Noise 10.3 Bandgap Reference Circuits 10.3.1 Bandgap Circuits in Bipolar Technology 10.3.2 Current-Mode Bandgap Circuit 10.3.3 Low-Voltage Bandgap Circuits 10.3.4 Second Order Compensation 10.4 Alternative References 10.4.1 Weak Inversion 10.4.2 DTMOST Reference Circuit 10.4.3 Other Technological Options Exercises References 11 Digital-to-Analog Conversion 11.1 Representations 11.1.1 Digital Codes 11.1.2 Unary Representation 11.1.3 Unary: INL and DNL 11.1.4 Binary Representation 11.1.5 Binary: INL and DNL 11.1.6 Segmentation 11.1.7 Segmented: INL and DNL 11.2 Voltage-Domain Digital-to-Analog Conversion 11.2.1 Resistor Ladders 11.2.2 Resistor Ladder: Dynamic Behavior 11.2.3 Practical Issues in Resistor Ladders 11.2.4 Accuracy in Resistors Ladders 11.2.5 R-2R Ladders 11.2.6 Accuracy in R-2R Ladders 11.2.7 A Video Resistor Ladder Digital-to-AnalogConverter 11.3 Current-Domain Digital-to-Analog Conversion 11.3.1 Buffered Current-Domain Digital-to-Analog Converters 11.3.2 Current-Steering Digital-to-Analog Conversion 11.3.3 Matrix Decoding 11.3.4 INL and DNL 11.3.5 Current Cell 11.3.6 Switching the Current Cells 11.3.7 Calibration of Current Sources 11.3.8 Sorting and Selecting 11.3.9 Performance Limits 11.3.10 Semi-Digital Filters 11.4 Charge-Domain Digital-to-Analog Conversion 11.4.1 Switched-Capacitor Digital-to-Analog Conversion 11.4.2 Charge-Redistribution Converters 11.4.3 RF Digital-to-Analog Converters 11.4.4 Bridge Capacitor 11.5 Algorithmic Digital-to-Analog Conversion 11.5.1 Conversion by Passive Redistribution 11.5.2 Diophantine Digital-to-Analog Conversion 11.6 Time-Domain Digital-to-Analog Conversion 11.6.1 1-Bit Digital-to-Analog Converter 11.6.2 Time-Domain Signals 11.6.3 Jitter in the Time Domain 11.6.4 Class-D Amplifiers Exercises References 12 Comparators 12.1 Comparator Classification 12.1.1 Limiting Amplifier 12.1.2 Hysteresis Comparator 12.1.3 Resistive Pre-amplification 12.1.4 Integrating Pre-amplification 12.1.5 Floating Inverter 12.1.6 Regenerative Comparator 12.1.7 Latch 12.2 Comparator Issues 12.2.1 Metastability and Bit Error Rate 12.2.2 Accuracy 12.2.3 Kick-Back 12.2.4 Hysteresis 12.3 Comparator Examples 12.3.1 Comparators: Amplifier Based 12.3.2 StrongARM Comparators 12.3.3 Double-Tail Comparator 12.3.4 Calibrated Comparators 12.3.5 T&H Plus Comparator Exercises References 13 Flash Analog-to-Digital Conversion 13.1 Classification of Analog-to-Digital Converters 13.2 Traditional Flash Converters 13.2.1 Ladder Implementation 13.2.2 Comparator Random Mismatch 13.2.3 Comparator Yield Loss 13.2.4 Decoder 13.3 Advanced Schemes 13.3.1 Averaging 13.3.2 Interpolation 13.3.3 Frequency Dependent Mismatch 13.3.4 Time Interpolation 13.3.5 Folding Converter 13.3.6 Mismatch Dominated Converter 13.3.7 Technology Scaling for Flash Converters 13.3.8 Digital Output Power 13.4 Power, Bandwidth, and Resolution Exercises References 14 Subranging and Two-Step Analog-to-Digital Conversion 14.1 Subranging Architecture 14.1.1 Overrange 14.1.2 Monkey-Switching 14.2 Two-Step Architecture 14.2.1 Overrange in Two-Step Architectures Exercises References 15 Pipeline Analog-to-Digital Conversion 15.1 1-Bit Pipeline Converters 15.1.1 Multiplying Digital-to-Analog Converter (MDAC) 15.1.2 MDAC Implementation 15.1.3 Error Sources in Pipeline Converters 15.1.4 Multiply-by-Two Errors 15.1.5 Bandwidth and Settling 15.1.6 Noise 15.1.7 Reduced Radix Converters with Calibration 15.2 1.5-Bit Pipeline Analog-to-Digital Converter 15.2.1 Redundancy 15.2.2 Design of an MDAC Stage 15.2.3 Multi-Bit MDAC Stage 15.3 Pipeline Variations 15.3.1 Opamp Sharing 15.3.2 Sample-and-Hold-Less Conversion 15.3.3 Decoupled Capacitors 15.3.4 Continuous-Time Front-End 15.3.5 Other Forms of MDAC Amplification 15.4 Algorithmic Converters 15.5 Power, Bandwidth, and Resolution Exercises References 16 Successive Approximation Conversion 16.1 The Algorithm 16.2 Charge-Redistribution Conversion 16.2.1 Basic Operation 16.2.2 Parasitic Capacitor 16.2.3 Top-Plate or Bottom-Plate Input 16.2.4 Bridge Capacitor 16.2.5 Digital Controller 16.3 Artifacts and Mitigations 16.3.1 Speed, Noise, and Kick-Back 16.3.2 Accuracy and Calibration 16.3.3 Redundancy for Comparator Errors 16.3.4 Sub-Radix-2 Base 16.3.5 Energy 16.4 Alternative Successive Approximation Converters 16.4.1 Two-Step Architectures with SAR 16.4.2 Passive Charge Division 16.4.3 Multi-Bit Comparison 16.4.4 Noise-Shaping SAR 16.4.5 Mismatch-Error Shaping 16.4.6 Resistive Successive Approximation Converter 16.4.7 Power, Bandwidth, and Resolution Exercises References 17 Linear and Time-Based Conversion 17.1 Linear Approximation Converters 17.1.1 Counting Converter 17.1.2 Tracking Converter 17.2 Time-Related Conversion 17.2.1 Wilkinson Converter 17.2.2 Dual-Slope Converter 17.2.3 Pulse-Width Modulation Converter 17.3 Voltage-to-Time Conversion 17.3.1 Voltage-to-Frequency Conversion 17.3.2 Time-to-Digital Conversion 17.3.3 Vernier/Nonius Principle 17.4 Other Conversion Proposals 17.4.1 Level-Crossing Analog-to-Digital Conversion 17.4.2 Asynchronous Successive ApproximationConversion 17.4.3 Floating-Point Converter References 18 Time-Interleaving 18.1 The Need for Time Interleaving 18.1.1 Time-Domain Interleaving 18.1.2 Frequency-Domain View 18.2 Input Sampling 18.2.1 1 Buffer 18.2.2 Input Driver 18.2.3 Signal Distribution 18.2.4 Track-and-Hold Implementations 18.3 Time-Interleaving Errors 18.3.1 Random DC-Offsets Between Channels 18.3.2 Random Gain Differences Between Channels 18.3.3 Input Sampling Errors 18.3.4 Bandwidth Differences 18.3.5 Reconstruction Errors 18.4 Time-Interleaving Architectures 18.4.1 2 Interleaving 18.4.2 3,4 Interleaving 18.4.3 8 Interleaving 18.4.4 Two-Stage Interleaving 18.5 Frequency Multiplexing 18.6 Power, Bandwidth, and Resolution Exercises References 19 Time-Discrete Modulation 19.1 Oversampling 19.1.1 Oversampling in Analog-to-Digital Conversion 19.1.2 Oversampling in Digital-to-Analog Conversion 19.2 Noise Shaping 19.2.1 Higher Order Noise Shaping 19.3 Modulation 19.3.1 A Quantizer in a Feedback Loop 19.3.2 Linearization 19.4 Time-Discrete Modulation 19.4.1 First Order Modulator 19.4.2 Second Order Modulator 19.4.3 Cascade of Integrators 19.4.4 Input Feed-Forward Modulator 19.4.5 Circuit Design Considerations 19.4.6 Overload 19.4.7 Decimation 19.5 Higher Order Time-Discrete Converters 19.5.1 Cascaded Modulator 19.5.2 0-L MASH 19.6 Digital-to-Analog Conversion 19.6.1 Single-Loop Conversion 19.6.2 Cascaded Digital-to-Analog Conversion Exercises References 20 Time-Continuous Modulation 20.1 First and Second Order Modulator 20.1.1 Linearized Model 20.1.2 Higher Order Converters 20.1.3 Digital-to-Analog Converter in the Loop 20.1.4 Excess Loop Delay in Time-Continuous Conversion 20.1.5 Meta-Stability 20.1.6 Latency 20.1.7 Filter Implementations 20.2 Time-Discrete and Time-Continuous Conversion 20.3 Multi-Bit Conversion 20.4 Various Forms of Modulation 20.4.1 First Order Modulator with Choppingand Dither 20.4.2 Complex Modulation 20.4.3 Asynchronous Modulation 20.4.4 Bandpass Converter 20.4.5 Loop with Noise-Shaping 20.4.6 Incremental Converter 20.5 Power, Bandwidth, and Resolution Exercises References 21 Mitigation of Errors 21.1 Strategies 21.2 Removing the Error 21.2.1 Auto-Zero Mechanism 21.2.2 Calibration 21.2.3 Split Converters 21.3 Moving the Error 21.3.1 Dithering 21.3.2 Chopping 21.3.3 Dynamic Element Matching (D.E.M.) 21.3.4 Data-Weighted Averaging (D.W.A.) Exercises References 22 Characterization and Measurement 22.1 Test Hardware 22.2 Measurement Methods 22.2.1 INL and DNL 22.2.2 Harmonic Behavior and Coherent Testing 22.2.3 Windowing 22.3 Special Measurements 22.3.1 Noise 22.3.2 Bit Error Rate 22.3.3 Multi-Tone Power Ratio 22.3.4 Differential Gain and Differential Phase 22.3.5 Self-Testing 22.4 How to Solve a Problem? Exercises References Index