دانلود کتاب Emerging devices for low-power and high-performance nanosystems: physics, novel functions, and data processing

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Content: Cover
Half Title
Title Page
Copyright Page
Table of Contents
Preface
Acknowledgments
Introduction: Cramming More Functions into Integrated Systems toward a Sustainable Information Technology World
PART I: HYBRID AND HETEROGENEOUS CMOS FOR ULTRA-LOW-POWER DATA PROCESSING
1: The Junctionless Transistor
1.1 Introduction
1.2 Junctionless MOSFET Operation and Properties
1.2.1 Device Physics
1.2.1.1 Effective channel length modulation
1.2.1.2 Mobility
1.2.1.3 Subthreshold slope
1.2.1.4 Threshold voltage and transconductance
1.2.1.5 Gate capacitance
1.2.1.6 Miller capacitance 1.2.1.7 Variability1.2.1.8 Reliability and noise
1.2.1.9 Bipolar effect
1.2.1.10 Models for the junctionless transistor
1.2.1.11 Carrier confinement effects
1.2.2 Junctionless Transistor Architectures
1.2.2.1 SOI trigate
1.2.2.2 SOI planar transistors
1.2.2.3 GAA
1.2.2.4 Vertical nanowire FETs
1.2.2.5 Bulk and stacked PN junctionless transistors
1.2.2.6 Tunnel FET
1.3 "Nonsilicon" Junctionless Transistors
1.3.1 Germanium
1.3.2 Polycrystalline Si and Ge
1.3.3 III-V Semiconductors
1.3.4 Other Materials
1.3.4.1 Transition metal dichalcogenides
1.3.4.2 Carbon nanotube transistors 1.3.4.3 Metal oxide transistors1.3.4.4 Metallic transistors
1.4 Junctionless Nanowire Sensors
1.5 Conclusions
2: Several Challenges in Steep-Slope Tunnel Field-Effect Transistors
2.1 Introduction
2.2 Challenges in Achieving Steep-Slope TFETs
2.2.1 Benchmarks of Realized Steep-Slope TFETs
2.2.2 Series Resistance
2.2.2.1 Contact resistance
2.2.2.2 Junction resistance
2.2.2.3 Channel resistance
2.2.3 Quality of MOS and Gate-Architecture
2.3 III-V/SI Heterointerface for a Tunnel Junction
2.3.1 Direct Integration of III-V NWs on Si/Ge 2.3.2 Misfit Dislocations at III-V NW/Si Junctions2.3.3 Diode Properties for the III-V NW/Si Junctions
2.4 Vertical Tunnel FETs Using a III-V/SI Junction
2.4.1 MOS Interface in Vertical InGaAs NW FETs
2.4.2 Degraded TFETs Using In(Ga)As NW/Si Junctions
2.4.3 Scaling of NW Diameter for a Steep SS
2.4.4 Challenges in Doping
2.4.4.1 Formation of an intrinsic layer in a III-V NW
2.4.4.2 Heavy doping
2.5 Challenges in Increasing the On-State Current
2.5.1 Effect of Channel Length
2.5.2 Effect on Strain
2.6 Conclusion
3: Nanoelectromechanical Switches
3.1 Introduction 3.1.1 Background: CMOS Energy Efficiency Limit3.1.2 Why Nanoscale Electromechanical Switches
3.2 Actuation Mechanisms
3.2.1 Electromagnetic
3.2.2 Electrothermal
3.2.3 Piezoelectric
3.2.4 Electrostatic
3.3 Electrostatic Relay Design for Digital Computing
3.3.1 Modeling and Analysis
3.3.1.1 Parallel-plate capacitor model
3.3.1.2 Operation modes
3.3.1.3 Hysteresis voltage
3.3.1.4 Mechanical delay
3.3.2 Challenges for Reducing Operating Voltage
3.4 Body-Biased Relay Technology
3.4.1 Relay Design and Fabrication Process
3.4.2 Scaling Theory
3.4.3 Recent Progress