دانلود کتاب Fundamentals of logic design

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Cover......Page 1
Title Page......Page 5
Copyright......Page 6
Brief Contents......Page 9
Contents......Page 11
Preface......Page 19
How to Use This Book for Self-Study......Page 24
About the Authors......Page 25
Objectives......Page 27
Study Guide......Page 28
1.1: Digital Systems and Switching Circuits......Page 32
1.2: Number Systems and Conversion......Page 34
1.3: Binary Arithmetic......Page 38
1.4: Representation of Negative Numbers......Page 42
1.5: Binary Codes......Page 47
Problems......Page 50
Objectives......Page 55
Study Guide......Page 56
2.1: Introduction......Page 62
2.2: Basic Operations......Page 63
2.3: Boolean Expressions and Truth Tables......Page 65
2.4: Basic Theorems......Page 67
2.5: Commutative, Associative, Distributive, and DeMorgan\'s Laws......Page 69
2.6: Simplification Theorems......Page 72
2.7: Multiplying out and Factoring......Page 75
2.8: Complementing Boolean Expressions......Page 78
Problems......Page 79
Objectives......Page 86
Study Guide......Page 87
3.1: Multiplying out and Factoring Expressions......Page 92
3.2: Exclusive-OR and Equivalence Operations......Page 94
3.3: The Consensus Theorem......Page 96
3.4: Algebraic Simplification of Switching Expressions......Page 98
3.5: Proving Validity of an Equation......Page 100
Programmed Exercise 3.2......Page 103
Programmed Exercise 3.3......Page 104
Programmed Exercise 3.4......Page 105
Programmed Exercise 3.5......Page 107
Problems......Page 108
Objectives......Page 113
Study Guide......Page 114
4.1: Conversion of English Sentences to Boolean Equations......Page 120
4.2: Combinational Logic Design Using a Truth Table......Page 122
4.3: Minterm and Maxterm Expansions......Page 123
4.4: General Minterm and Maxterm Expansions......Page 126
4.5: Incompletely Specified Functions......Page 129
4.6: Examples of Truth Table Construction......Page 130
4.7: Design of Binary Adders and Subtracters......Page 134
Problems......Page 140
Objectives......Page 149
Study Guide......Page 150
5.1: Minimum Forms of Switching Functions......Page 160
5.2: Two- and Three-Variable Karnaugh Maps......Page 162
5.3: Four-Variable Karnaugh Maps......Page 167
5.4: Determination of Minimum Expressions Using Essential Prime Implicants......Page 170
5.5: Five-Variable Karnaugh Maps......Page 175
5.6: Other Uses of Karnaugh Maps......Page 178
5.7: Other Forms of Karnaugh Maps......Page 179
Programmed Exercise 5.1......Page 180
Programmed Exercise 5.2......Page 182
Problems......Page 185
Objectives......Page 193
Study Guide......Page 194
6.1: Determination of Prime Implicants......Page 199
6.2: The Prime Implicant Chart......Page 202
6.3: Petrick\'s Method......Page 205
6.4: Simplification of Incompletely Specified Functions......Page 207
6.5: Simplification Using Map-Entered Variables......Page 208
6.6: Conclusion......Page 210
Programmed Exercise 6.1......Page 211
Problems......Page 215
Objectives......Page 219
Study Guide......Page 220
7.1: Multi-Level Gate Circuits......Page 225
7.2: NAND and NOR Gates......Page 230
7.3: Design of Two-Level NAND- and NOR-Gate Circuits......Page 232
7.4: Design of Multi-Level NAND- and NOR-Gate Circuits......Page 235
7.5: Circuit Conversion Using Alternative Gate Symbols......Page 236
7.6: Design of Two-Level, Multiple-Output Circuits......Page 240
7.7: Multiple-Output NAND- and NOR-Gate Circuits......Page 243
Problems......Page 244
Objectives......Page 251
Study Guide......Page 252
8.1: Review of Combinational Circuit Design......Page 255
8.2: Design of Circuits with Limited Gate Fan-In......Page 256
8.3: Gate Delays and Timing Diagrams......Page 258
8.4: Hazards in Combinational Logic......Page 260
8.5: Simulation and Testing of Logic Circuits......Page 266
Problems......Page 269
Objectives......Page 278
Study Guide......Page 279
9.1: Introduction......Page 286
9.2: Multiplexers......Page 287
9.3: Three-State Buffers......Page 291
9.4: Decoders and Encoders......Page 294
9.5: Read-Only Memories......Page 297
9.6: Programmable Logic Devices......Page 301
9.7: Complex Programmable Logic Devices......Page 306
9.8: Field-Programmable Gate Arrays......Page 308
Problems......Page 312
Objectives......Page 320
Study Guide......Page 321
10.1: VHDL Description of Combinational Circuits......Page 325
10.2: VHDL Models for Multiplexers......Page 330
10.3: VHDL Modules......Page 332
10.4: Signals and Constants......Page 337
10.5: Arrays......Page 338
10.6: VHDL Operators......Page 341
10.7: Packages and Libraries......Page 342
10.8: IEEE Standard Logic......Page 344
10.9: Compilation and Simulation of VHDL Code......Page 347
Problems......Page 348
Design Problems......Page 353
Objectives......Page 357
Study Guide......Page 358
11.1: Introduction......Page 362
11.2: Set-Reset Latch......Page 364
11.3: Gated Latches......Page 368
11.4: Edge-Triggered D Flip-Flop......Page 372
11.5: S-R Flip-Flop......Page 375
11.6: J-K Flip-Flop......Page 376
11.7: T Flip-Flop......Page 377
11.8: Flip-Flops with Additional Inputs......Page 378
11.9: Asynchronous Sequential Circuits......Page 380
11.10: Summary......Page 383
Problems......Page 384
Programmed Exercise 11.35......Page 393
Objectives......Page 396
Study Guide......Page 397
12.1: Registers and Register Transfers......Page 402
12.2: Shift Registers......Page 406
12.3: Design of Binary Counters......Page 410
12.4: Counters for Other Sequences......Page 415
12.5: Counter Design Using S-R and J-K Flip-Flops......Page 421
12.6: Derivation of Flip-Flop Input Equations - Summary......Page 424
Problems......Page 428
Objectives......Page 438
Study Guide......Page 439
13.1: A Sequential Parity Checker......Page 445
13.2: Analysis by Signal Tracing and Timing Charts......Page 447
13.3: State Tables and Graphs......Page 451
13.4: General Models for Sequential Circuits......Page 458
Programmed Exercise 13.1......Page 462
Problems......Page 467
Objectives......Page 479
Study Guide......Page 480
14.1: Design of a Sequence Detector......Page 483
14.2: More Complex Design Problems......Page 489
14.3: Guidelines for Construction of State Graphs......Page 493
14.4: Serial Data Code Conversion......Page 499
14.5: Alphanumeric State Graph Notation......Page 502
14.6: Incompletely Specified State Tables......Page 504
Programmed Exercise 14.1......Page 506
Programmed Exercise 14.2......Page 508
Programmed Exercise 14.3......Page 510
Problems......Page 512
Objectives......Page 523
Study Guide......Page 524
15.1: Elimination of Redundant States......Page 531
15.2: Equivalent States......Page 533
15.3: Determination of State Equivalence Using an Implication Table......Page 535
15.4: Equivalent Sequential Circuits......Page 538
15.5: Reducing Incompletely Specified State Tables......Page 540
15.6: Derivation of Flip-Flop Input Equations......Page 543
15.7: Equivalent State Assignments......Page 545
15.8: Guidelines for State Assignment......Page 549
15.9: Using a One-Hot State Assignment......Page 554
Problems......Page 557
Objectives......Page 571
Study Guide......Page 572
16.1: Summary of Design Procedure for Sequential Circuits......Page 574
16.2: Design Example - Code Converter......Page 575
16.3: Design of Iterative Circuits......Page 579
16.4: Design of Sequential Circuits Using ROMs and PLAs......Page 582
16.5: Sequential Circuit Design Using CPLDs......Page 585
16.6: Sequential Circuit Design Using FPGAs......Page 589
16.7: Simulation and Testing of Sequential Circuits......Page 591
16.8: Overview of Computer-Aided Design......Page 596
Design Problems......Page 598
Additional Problems......Page 604
Objectives......Page 611
Study Guide......Page 612
17.1: Modeling Flip-Flops Using VHDL Processes......Page 616
17.2: Modeling Registers and Counters Using VHDL Processes......Page 620
17.3: Modeling Combinational Logic Using VHDL Processes......Page 625
17.4: Modeling a Sequential Machine......Page 627
17.5: Synthesis of VHDL Code......Page 634
17.6: More about Processes and Sequential Statements......Page 637
Problems......Page 639
Simulation Problems......Page 650
Objectives......Page 652
Study Guide......Page 653
18.1: Serial Adder with Accumulator......Page 655
18.2: Design of a Binary Multiplier......Page 659
18.3: Design of a Binary Divider......Page 663
Programmed Exercise 18.1......Page 670
Programmed Exercise 18.2......Page 672
Problems......Page 674
Objectives......Page 686
Study Guide......Page 687
19.1: State Machine Charts......Page 688
19.2: Derivation of SM Charts......Page 693
19.3: Realization of SM Charts......Page 698
Problems......Page 703
Objectives......Page 710
Study Guide......Page 711
20.1: VHDL Code for a Serial Adder......Page 714
20.2: VHDL Code for a Binary Multiplier......Page 716
20.3: VHDL Code for a Binary Divider......Page 726
20.4: VHDL Code for a Dice Game Simulator......Page 728
20.5: Concluding Remarks......Page 731
Problems......Page 732
Lab Design Problems......Page 735
Appendix A: MOS and CMOS Logic......Page 739
Appendix B: VHDL Language Summary......Page 745
Appendix C: Tips for Writing Synthesizable VHDL Code......Page 750
Appendix D: Proofs of Theorems......Page 753
Appendix E: Answers to Selected Study Guide Questions and Problems......Page 755
References......Page 811
Index......Page 812
Description of the CD......Page 818