دانلود کتاب JEDEC STANDARD. Wide I/O 2 (WideIO2). JESD229-2

فهرست مطالب :

1 Scope
2 General Description
2.1 Terms and Definitions
2.2 Key Features
2.3 Bandwidth vs. Capacity Relationship
Table 1 — Capacity vs. Bandwidth (8 - 32Gb Die Density)
2.4 WideIO2 Topologies
2.4.1 WideIO2 Topologies with 4x64 Die
2.4.1.1 1-High 4Ch x 64b
2.4.1.2 2-High 8Ch x 64b Capacity and Bandwidth Scaling
2.4.1.3 4-High, 8Ch x 64b, P22P Capacity and Bandwidth Scaling
2.4.2 WideIO2 Topologies with 8x64 Die
2.4.2.1 1-High 8Ch x 64b
2.4.2.2 2-High 8Ch x 64b
2.5 Micropillar-out
2.5.1 Micropillar Definition and Description
Table 2 — Micropillar Definition and Description
2.5.2 Quadrant Micropillars
Table 3 — Micropillar Definitions (Per Quadrant)
2.5.3 Channel Interface Signals
Table 4 — Channel Interface Signals
Table 5 — DQS and DMI Mapping
2.5.4 CKE and CS Mapping
Table 6 — CKE and CS Mapping
2.5.5 Test Sub-Block Micropillar Signals
Table 7 — Test Sub-Block Micropillar Signals
2.5.6 Bump Plan
2.6 TSV Signal Routing
Table 8 — TSV Signal Routing for 4ch x64b
Table 9 — TSV Signal Routing for 8ch x64b
2.6.1 Micropillar Locations
2.7 Addressing
2.7.1 Addressing for 4x64 Die
Table 10 — Address Table (4x64 Die)
2.7.2 Addressing for 8x64 Die
Table 11 — Address Table (8x64 Die)
3 Functional Descriptions
3.1 State Diagram
3.2 Power-up, Initialization, and Power-off
3.2.1 Voltage Ramp and Device Initialization
Table 12 — Voltage Ramp Conditions
Table 13 — Initialization Timing Parameters
3.2.2 Reset Initialization with stable power
Table 14 — Timing Parameters for Reset Initialization with stable Power
3.2.3 Power-off Sequence
Table 15 — Power Supply Conditions
3.2.4 Uncontrolled Power-Off Sequence
Table 16 — Timing Parameters Power-Off
3.3 Input Clock Stop and Frequency Change
3.4 Mode Register Definition
Table 17 — Mode Register Assignment in WideIO2 SDRAM
3.4.1 MR0_Reserved (MA<7:0> = 00H)
3.4.2 MR1_Device Feature 1 (MA<7:0> = 01H)
Table 18 — Burst Sequence
3.4.3 MR2_Device Feature 2 (MA<7:0> = 02H)
3.4.4 MR3_I/O Configuration 1 (MA<7:0> = 03H)
3.4.4.1 Thermal Offset
3.4.5 MR4_Device Temperature (MA<7:0> = 04H)
3.4.5.1 Temperature Sensor
Table 19 — Temperature Sensor
3.4.6 MR5_Basic Configuration 1 (MA<7:0> = 05H)
3.4.7 MR6_Basic Configuration 2 (MA<7:0> = 06H)
3.4.8 MR7_Basic Configuration 3 (MA<7:0> = 07H)
3.4.9 MR8_Basic Configuration 4 (MA<7:0> = 08H)
3.4.10 MR9_Test Mode (MA<7:0> = 09H)
3.4.11 MR10_Reserved (MA<7:0> = 0AH)
3.4.12 MR11_PASR-1 (MA<7:0> = 0BH)
3.4.13 MR12_PASR-2 (MA<7:0> = 0CH)
3.4.14 MR13_Post Package Repair Resource (MA<7:0> = 0DH)
3.4.15 MR14_TRR-1 (MA<7:0> = 0EH)
3.4.16 MR15_TRR-2 (MA<7:0> = 0FH)
4 Command Definitions and Timing
4.1 Command Truth Table
Table 20 — Command Truth Table
4.2 Activate Command
4.2.1 Device Operation
4.3 Read And Write Access Modes
4.4 Read Command
4.4.1 Burst Read Command
4.4.2 Back-to-Back Reads from Different Ranks
4.4.3 Read preamble
4.5 Write command
4.5.1 Burst Write Command
4.5.2 Write Preamble
4.6 Masked Write Command
4.6.1 Masked Write Timing Constraints
4.6.1.1 Same bank
4.6.1.2 Different bank
4.7 WideIO2 Data Mask (DM) and Data Bus Inversion (DBIac) Function
Table 21 — Odd/Even Byte Groups
4.7.1 DBIac States (Either Write/Masked Write DBIac or Read DBIac is enabled)
4.7.1.1 Write Operation
4.7.1.2 Masked Write Operation
4.7.1.3 Read Operation
4.7.1.4 Mode Register Read (MRR) Operation
4.7.2 DM and DBIac Function Combinations
Table 22 — Function Behavior of DMI Signal During Write, Masked Write and Read Operation
Table 23 — DBIac Algorithm during Write Command
Table 24 — DBIac Algorithm During Masked Write Command - Example 1
Table 25 — DBIac Algorithm During Masked Write Command - Example 2
Table 26 — DBIac Algorithm During Write Command Followed by Masked Write Command
4.8 Refresh Command
Table 27 — REFRESH Command Scheduling Separation Requirements
Table 28 — Legacy REFRESH Command Timing Constraints
Table 29 — Modified REFRESH Command Timing Constraints
4.8.1 Refresh Requirements
4.8.1.1 Minimum number of REFRESH commands
4.8.1.2 REFRESH Requirements and SELF REFRESH
Table 30 — Refresh Requirements
4.9 Power Down
4.10 Self Refresh Operation
4.10.1 Self-Refresh Abort
4.11 Partial Array Self Refresh
4.11.1 PASR Bank Masking
4.11.2 PASR Segment Masking
Table 31 — Example of Bank and Segment Masking use in WIO2 devices
4.12 TRR Mode - Target Row Refresh
4.13 Precharge Operation
Table 32 — Bank selection for Precharge by address bits
4.13.1 Burst Read followed by Precharge
4.13.2 Burst Write followed by Precharge
4.13.3 Auto Precharge operation
4.13.4 Burst Read with Auto-Precharge
4.13.5 Burst Write with Auto-Precharge
Table 33 — Precharge & Auto Precharge clarification
4.14 Mode Register Read (MRR) Command
4.14.1 MRR Following Idle Power-Down State
4.15 Mode Register Write (MRW) Command
4.15.1 MRR and MRW Restrictions
Table 34 — Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW)
4.16 Deselect and No Operation Command
5 WideIO2 Boundary Scan Interface
5.1 Overview
5.2 Slice and Stack Level Configuration
5.3 Within-Slice Scan Chain Configuration and Operation
Table 35 — Boundary Scan Truth Table
5.4 Boundary Scan Operational Timing Diagram
5.5 Test Area Micro-Bump Assignments
5.6 Boundary Scan AC Timing
Table 36 — Boundary Scan AC Timings
5.7 Boundary Scan Chain Order
5.7.1 4x64 Die Boundary Scan Chain Order
Table 37 — 4x64 Die Boundary Scan Exit Order (Quadrant A)
5.7.2 8x64 Die Boundary Scan Chain Order
Table 38 — 8x64 Die Boundary Scan Exit Order (Quadrant A)
6 General Purpose IO Test Mode
7 Post Package Repair (PPR)
7.1 Fail Row Address Repair
Table 40 — PPR Setting
7.2 Programming PPR support in MR13
7.3 Required Timing Parameters
Table 41 — PPR Timing Parameters
8 AC & DC Operating Conditions
8.1 Absolute Maximum DC Rating
8.2 DC Operating Conditions
Table 42 — DC operating conditions
8.3 Input Leakage Current
Table 43 — Input Leakage Current
8.4 Operating Temperature
Table 44 — Operating Temperature
9 AC and DC Input Specifications
9.1 AC and DC Input Measurement Levels
Table 45 — Receiver Input Voltage Level Specification
10 AC and DC Output Specifications
10.1 Output Timing Reference Load
Table 46 — Output Timing Reference Load
10.2 Definition of Output Voltage Levels and Output Rise/Fall Times (TR, TF)
Table 47 — Transmitter Output Voltage Level Specification
Table 48 — Output Rise/Fall Time Measurement Definition
Table 49 — Transmitter Output Rise/Fall Time Specification
10.3 Over/Undershoot
Table 50 — Over/Undershoot
11 Input/Output Capacitance
12 Electrical Characteristics and AC Timings
12.1 Command input signal timing definition
12.1.1 Command input signal timing definition for CS_n
12.1.2 Command input signal timing definition for CA
12.1.3 Command input signal timing definition for CKE
12.2 Clock Specification
12.2.1 Definition for tCK(avg) and nCK
12.2.2 Definition for tCK(abs)
12.2.3 Definition for tCHH(avg), tCHM(avg), tCLL(avg) and tCLM(avg)
12.2.4 Definition for tJIT(per)
12.2.5 Definition for tJIT(cc)
12.2.6 Definition for tERR(nper)
12.2.7 Definition for duty cycle jitter tJIT(duty)
12.2.8 Definition for tCK(abs), tCHM(abs) and tCLM(abs)
Table 52 — Definition for tCK(abs), tCHM(abs), tCLM(abs)
12.3 Period Clock Jitter
12.3.1 Clock period jitter effects on core timing parameters (tRCD, tRP, tRTP, tWR, tWTR, tRC, tRAS, tRRD, tFAW )
12.3.1.1 Cycle time de-rating for core timing parameters
12.3.1.2 Clock Cycle de-rating for core timing parameters
12.3.2 Clock jitter effects on Command/Address timing parameters (tISCA, tIHCA, tISCS, tIHCS,tISCKE, tIHCKE, tISb, tIHb, tISCKEb, tIHCKEb)
12.3.3 Clock jitter effects on Read timing parameters
12.3.3.1 tRPRE
12.3.3.2 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)
12.3.4 Clock jitter effects on Write timing parameters
12.3.4.1 tDS, tDH
12.3.5 tDSS, tDSH
12.3.5.1 tDQSS
12.4 AC Timing Definitions
12.5 AC Timings
Table 53 — AC Timings
13 IDD Specification Parameter and Test Condition
13.1 IDD Specifications
Table 54 — IDD Specification Parameters
13.2 IDD Measurement Conditions
Table 55 — Definition of Switching for CA Input Signals
Table 56 — Definition of Switching for IDD4R
Table 57 — Definition of Switching for IDD4W