دانلود کتاب NAND Flash Memory Technologies

فهرست مطالب :

Content: IEEE Press
TitlePage
Copyright
Foreword
Preface
Acknowledgments
About the Author
1 Introduction
1.1 Background
1.2 Overview
References
2 Principle of NAND Flash Memory
2.1 NAND Flash Device and Architecture
2.2 Cell Operation
2.3 Multilevel Cell (MLC)
References
3 NAND Flash Memory Devices
3.1 Introduction
3.2 LOCOS Cell
3.3 Self-Aligned STI Cell (SA-STI Cell) with FG Wing
3.4 Self-Aligned STI Cell (SA-STI Cell) without FG Wing
3.5 Planar FG Cell
3.6 SideWall Transfer Transistor Cell (SWATT Cell)
3.7 Advanced NAND Flash Device Technologies
References 4 Advanced Operation for Multilevel Cell4.1 Introduction
4.2 Program Operation for Tight Vt Distribution Width
4.3 Page Program Sequence
4.4 TLC (3 Bits/Cell)
4.5 QLC (4 Bits/Cell)
4.6 Three-Level (1.5 bits/cell) NAND flash
4.7 Moving Read Algorithm
References
5 Scaling Challenge of NAND Flash Memory Cells
5.1 Introduction
5.2 Read Window Margin (RWM)
5.3 Floating-Gate Capacitive Coupling Interference
5.4 Program Electron Injection Spread
5.5 Random Telegraph Signal Noise (RTN)
5.6 Cell Structure Challenge
5.7 High-Field Limitation
5.8 A few electron phenomena 5.9 Patterning Limitation5.10 Variation
5.11 Scaling impact on Data Retention
5.12 Summary
References
6 Reliability of NAND Flash Memory
6.1 Introduction
6.2 Program/Erase Cycling Endurance and Data Retention
6.3 Analysis of Program/Erase Cycling Endurance and Data Retention
6.4 Read Disturb
6.5 Program Disturb
6.6 Erratic Over-Program
6.7 Negative Vt shift phenomena
6.8 Summary
References
7 Three-Dimensional NAND Flash Cell
7.1 Background of Three-Dimensional NAND cells
7.2 BiCS (Bit Cost Scalable technology) / P-BiCS (Pipe-shape BiCS) 7.3 TCAT (Terabit Cell Array Transistor)/V-NAND (Vertical-NAND)7.4 SMArT (Stacked Memory Array Transistor)
7.5 VG-NAND (Vertical Gate NAND Cell)
7.6 Dual Control gate-Surrounding Floating gate Cell (DC-SF cell)
7.7 Advanced DC-SF cell
References
8 Challenges of Three-Dimensional NAND Flash Memory
8.1 Introduction
8.2 Comparison of 3D NAND cells
8.3 Data Retention
8.4 Program Disturb
8.5 Word-Line RC delay
8.6 Cell Current Fluctuation
8.7 Number of Stacked Cells
8.8 Peripheral Circuit Under Cell Array
8.9 Power Consumption
8.10 Future Trend of 3D NAND Flash Memory
References 9 Conclusions9.1 Discussions and conclusions
9.2 Perspective
References
Index
IEEE Press Series on Microelectronic Systems
EULA