دانلود کتاب PCI Express Base Specification, Revision 4.0, Version 0.3 (Change Bar)

فهرست مطالب :

PCI Express® Base Specification Revision 4.0 Version 0.3 February 19, 2014
Preface
Objective of the Specification
Document Organization
Documentation Conventions
Terms and Acronyms
Reference Documents
1. Introduction
1.1. A Third Generation I/O Interconnect
1.2. PCI Express Link
1.3. PCI Express Fabric Topology
1.3.1. Root Complex
1.3.2. Endpoints
1.3.2.1. Legacy Endpoint Rules
1.3.2.2. PCI Express Endpoint Rules
1.3.2.3. Root Complex Integrated Endpoint Rules
1.3.3. Switch
1.3.4. Root Complex Event Collector
1.3.5. PCI Express to PCI/PCI-X Bridge
1.4. PCI Express Fabric Topology Configuration
1.5. PCI Express Layering Overview
1.5.1. Transaction Layer
1.5.2. Data Link Layer
1.5.3. Physical Layer
1.5.4. Layer Functions and Services
1.5.4.1. Transaction Layer Services
1.5.4.2. Data Link Layer Services
1.5.4.3. Physical Layer Services
1.5.4.4. Inter-Layer Interfaces
1.5.4.4.1. Transaction/Data Link Interface
1.5.4.4.2. Data Link/Physical Interface
2. Transaction Layer Specification
2.1. Transaction Layer Overview
2.1.1. Address Spaces, Transaction Types, and Usage
2.1.1.1. Memory Transactions
2.1.1.2. I/O Transactions
2.1.1.3. Configuration Transactions
2.1.1.4. Message Transactions
2.1.2. Packet Format Overview
2.2. Transaction Layer Protocol - Packet Definition
2.2.1. Common Packet Header Fields
2.2.2. TLPs with Data Payloads - Rules
2.2.3. TLP Digest Rules
2.2.4. Routing and Addressing Rules
2.2.4.1. Address Based Routing Rules
2.2.4.2. ID Based Routing Rules
2.2.5. First/Last DW Byte Enables Rules
2.2.6. Transaction Descriptor
2.2.6.1. Overview
2.2.6.2. Transaction Descriptor – Transaction ID Field
2.2.6.3. Transaction Descriptor – Attributes Field
2.2.6.4. Relaxed Ordering and ID-Based Ordering Attributes
2.2.6.5. No Snoop Attribute
2.2.6.6. Transaction Descriptor – Traffic Class Field
2.2.7. Memory, I/O, and Configuration Request Rules
2.2.7.1. TPH Rules
2.2.8. Message Request Rules
2.2.8.1. INTx Interrupt Signaling - Rules
2.2.8.2. Power Management Messages
2.2.8.3. Error Signaling Messages
2.2.8.4. Locked Transactions Support
2.2.8.5. Slot Power Limit Support
2.2.8.6. Vendor_Defined Messages
2.2.8.6.1. PCI-SIG-Defined VDMs
2.2.8.6.2. LN Messages
2.2.8.6.3. Device Readiness Status (DRS) Message
2.2.8.6.4. Function Readiness Status (FRS) Message
2.2.8.7. Ignored Messages
2.2.8.8. Latency Tolerance Reporting (LTR) Message
2.2.8.9. Optimized Buffer Flush/Fill (OBFF) Message
2.2.8.10. Precision Time Measurement (PTM) Messages
2.2.9. Completion Rules
2.2.10. TLP Prefix Rules
2.2.10.1. Local TLP Prefix Processing
2.2.10.1.1. Vendor Defined Local TLP Prefix
2.2.10.2. End-End TLP Prefix Processing
2.2.10.2.1. Vendor Defined End-End TLP Prefix
2.2.10.2.2. Root Ports with End-End TLP Prefix Supported
2.3. Handling of Received TLPs
2.3.1. Request Handling Rules
2.3.1.1. Data Return for Read Requests
2.3.2. Completion Handling Rules
2.4. Transaction Ordering
2.4.1. Transaction Ordering Rules
2.4.2. Update Ordering and Granularity Observed by a Read Transaction
2.4.3. Update Ordering and Granularity Provided by a Write Transaction
2.5. Virtual Channel (VC) Mechanism
2.5.1. Virtual Channel Identification (VC ID)
2.5.2. TC to VC Mapping
2.5.3. VC and TC Rules
2.6. Ordering and Receive Buffer Flow Control
2.6.1. Flow Control Rules
2.6.1.1. FC Information Tracked by Transmitter
2.6.1.2. FC Information Tracked by Receiver
2.7. Data Integrity
2.7.1. ECRC Rules
2.7.2. Error Forwarding
2.7.2.1. Error Forwarding Usage Model
2.7.2.2. Rules For Use of Data Poisoning
2.8. Completion Timeout Mechanism
2.9. Link Status Dependencies
2.9.1. Transaction Layer Behavior in DL_Down Status
2.9.2. Transaction Layer Behavior in DL_Up Status
2.9.3. Transaction Layer Behavior During Downstream Port Containment
3. Data Link Layer Specification
3.1. Data Link Layer Overview
3.2. Data Link Control and Management State Machine
3.2.1. Data Link Control and Management State Machine Rules
3.3. Flow Control Initialization Protocol
3.3.1. Flow Control Initialization State Machine Rules
3.4. Data Link Layer Packets (DLLPs)
3.4.1. Data Link Layer Packet Rules
3.5. Data Integrity
3.5.1. Introduction
3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter)
3.5.2.1. LCRC and Sequence Number Rules (TLP Transmitter)
3.5.2.2. Handling of Received DLLPs
3.5.3. LCRC and Sequence Number (TLP Receiver)
3.5.3.1. LCRC and Sequence Number Rules (TLP Receiver)
4. Physical Layer Specification
4.1. Introduction
4.2. Logical Sub-block
4.2.1. Encoding for 2.5 GT/s and 5.0 GT/s Data Rates
4.2.1.1. Symbol Encoding
4.2.1.1.1. Serialization and De-serialization of Data
4.2.1.1.2. Special Symbols for Framing and Link Management (K Codes)
4.2.1.1.3. 8b/10b Decode Rules
4.2.1.2. Framing and Application of Symbols to Lanes
4.2.1.3. Data Scrambling
4.2.2. Encoding for 8.0 GT/s and Higher Data Rates
4.2.2.1. Lane Level Encoding
4.2.2.2. Ordered Set Blocks
4.2.2.2.1. Block Alignment
4.2.2.3. Data Blocks
4.2.2.3.1. Framing Tokens
4.2.2.3.2. Transmitter Framing Requirements
4.2.2.3.3. Receiver Framing Requirements
4.2.2.3.4. Recovery from Framing Errors
4.2.2.4. Scrambling
4.2.2.5. Loopback with 128b/130b Code
4.2.3. Link Equalization Procedure for 8.0 GT/s and Higher Data Rates
4.2.3.1. Rules for Transmitter Coefficients
4.2.3.2. Encoding of Presets
4.2.4. Link Initialization and Training
4.2.4.1. Training Sequences
4.2.4.2. Electrical Idle Sequences
4.2.4.3. Inferring Electrical Idle
4.2.4.4. Lane Polarity Inversion
4.2.4.5. Fast Training Sequence (FTS)
4.2.4.6. Start of Data Stream Ordered Set
4.2.4.7. Link Error Recovery
4.2.4.8. Reset
4.2.4.8.1. Fundamental Reset
4.2.4.8.2. Hot Reset
4.2.4.9. Link Data Rate Negotiation
4.2.4.10. Link Width and Lane Sequence Negotiation
4.2.4.10.1. Required and Optional Port Behavior
4.2.4.11. Lane-to-Lane De-skew
4.2.4.12. Lane vs. Link Training
4.2.5. Link Training and Status State Machine (LTSSM) Descriptions
4.2.5.1. Detect
4.2.5.2. Polling
4.2.5.3. Configuration
4.2.5.4. Recovery
4.2.5.5. L0
4.2.5.6. L0s
4.2.5.7. L1
4.2.5.8. L2
4.2.5.9. Disabled
4.2.5.10. Loopback
4.2.5.11. Hot Reset
4.2.6. Link Training and Status State Rules
4.2.6.1. Detect
4.2.6.1.1. Detect.Quiet
4.2.6.1.2. Detect.Active
4.2.6.2. Polling
4.2.6.2.1. Polling.Active
4.2.6.2.2. Polling.Compliance
4.2.6.2.3. Polling.Configuration
4.2.6.2.4. Polling.Speed
4.2.6.3. Configuration
4.2.6.3.1. Configuration.Linkwidth.Start
4.2.6.3.1.1. Downstream Lanes
4.2.6.3.1.2. Upstream Lanes
4.2.6.3.2. Configuration.Linkwidth.Accept
4.2.6.3.2.1. Downstream Lanes
4.2.6.3.2.2. Upstream Lanes
4.2.6.3.3. Configuration.Lanenum.Accept
4.2.6.3.3.1. Downstream Lanes
4.2.6.3.3.2. Upstream Lanes
4.2.6.3.4. Configuration.Lanenum.Wait
4.2.6.3.4.1. Downstream Lanes
4.2.6.3.4.2. Upstream Lanes
4.2.6.3.5. Configuration.Complete
4.2.6.3.5.1. Downstream Lanes
4.2.6.3.5.2. Upstream Lanes
4.2.6.3.6. Configuration.Idle
4.2.6.4. Recovery
4.2.6.4.1. Recovery.RcvrLock
4.2.6.4.2. Recovery.Equalization
4.2.6.4.2.1 Downstream Lanes
4.2.6.4.2.1.1. Phase 1 of Transmitter Equalization
4.2.6.4.2.1.2. Phase 2 of Transmitter Equalization
4.2.6.4.2.1.3. Phase 3 of Transmitter Equalization
4.2.6.4.2.2 Upstream Lanes
4.2.6.4.2.2.1. Phase 0 of Transmitter Equalization
4.2.6.4.2.2.2. Phase 1 of Transmitter Equalization
4.2.6.4.2.2.3. Phase 2 of Transmitter Equalization
4.2.6.4.2.2.4. Phase 3 of Transmitter Equalization
4.2.6.4.3. Recovery.Speed
4.2.6.4.4. Recovery.RcvrCfg
4.2.6.4.5. Recovery.Idle
4.2.6.5. L0
4.2.6.6. L0s
4.2.6.6.1. Receiver L0s
4.2.6.6.1.1. Rx_L0s.Entry
4.2.6.6.1.2. Rx_L0s.Idle
4.2.6.6.1.3. Rx_L0s.FTS
4.2.6.6.2. Transmitter L0s
4.2.6.6.2.1. Tx_L0s.Entry
4.2.6.6.2.2. Tx_L0s.Idle
4.2.6.6.2.3. Tx_L0s.FTS
4.2.6.7. L1
4.2.6.7.1. L1.Entry
4.2.6.7.2. L1.Idle
4.2.6.8. L2
4.2.6.8.1. L2.Idle
4.2.6.8.2. L2.TransmitWake
4.2.6.9. Disabled
4.2.6.10. Loopback
4.2.6.10.1. Loopback.Entry
4.2.6.10.2. Loopback.Active
4.2.6.10.3. Loopback.Exit
4.2.6.11. Hot Reset
4.2.7. Clock Tolerance Compensation
4.2.7.1. SKP Ordered Set for 8b/10b Encoding
4.2.7.2. SKP Ordered Set for 128b/130b Encoding
4.2.7.3. Rules for Transmitters
4.2.7.4. Rules for Receivers
4.2.8. Compliance Pattern in 8b/10b Encoding
4.2.9. Modified Compliance Pattern in 8b/10b Encoding
4.2.10. Compliance Pattern in 128b/130b Encoding
4.2.11. Modified Compliance Pattern in 128b/130b Encoding
5. Power Management
5.1. Overview
5.1.1. Statement of Requirements
5.2. Link State Power Management
5.3. PCI-PM Software Compatible Mechanisms
5.3.1. Device Power Management States (D-States) of a Function
5.3.1.1. D0 State
5.3.1.2. D1 State
5.3.1.3. D2 State
5.3.1.4. D3 State
5.3.1.4.1. D3hot State
5.3.1.4.2. D3cold State
5.3.2. PM Software Control of the Link Power Management State
5.3.2.1. Entry into the L1 State
5.3.2.2. Exit from L1 State
5.3.2.3. Entry into the L2/L3 Ready State
5.3.3. Power Management Event Mechanisms
5.3.3.1. Motivation
5.3.3.2. Link Wakeup
5.3.3.2.1. PME Synchronization
5.3.3.3. PM_PME Messages
5.3.3.3.1. PM_PME “Backpressure” Deadlock Avoidance
5.3.3.4. PME Rules
5.3.3.5. PM_PME Delivery State Machine
5.4. Native PCI Express Power Management Mechanisms
5.4.1. Active State Power Management (ASPM)
5.4.1.1. L0s ASPM State
5.4.1.1.1. Entry into the L0s State
5.4.1.1.2. Exit from the L0s State
5.4.1.2. L1 ASPM State
5.4.1.2.1. Entry into the L1 State
5.4.1.2.2. Exit from the L1 State
5.4.1.3. ASPM Configuration
5.4.1.3.1. Software Flow for Enabling or Disabling ASPM
5.5. L1 PM Substates
5.5.1. Entry conditions for L1 PM Substates and L1.0 Requirements
5.5.2. L1.1 Requirements
5.5.2.1. Exit from L1.1
5.5.3. L1.2 Requirements
5.5.3.1. L1.2.Entry
5.5.3.2. L1.2.Idle
5.5.3.3. L1.2.Exit
5.5.3.3.1. Exit from L1.2
5.5.4. L1 PM Substates Configuration
5.5.5. L1 PM Substates Timing Parameters
5.6. Auxiliary Power Support
5.6.1. Auxiliary Power Enabling
5.7. Power Management System Messages and DLLPs
6. System Architecture
6.1. Interrupt and PME Support
6.1.1. Rationale for PCI Express Interrupt Model
6.1.2. PCI Compatible INTx Emulation
6.1.3. INTx Emulation Software Model
6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support
6.1.5. PME Support
6.1.6. Native PME Software Model
6.1.7. Legacy PME Software Model
6.1.8. Operating System Power Management Notification
6.1.9. PME Routing Between PCI Express and PCI Hierarchies
6.2. Error Signaling and Logging
6.2.1. Scope
6.2.2. Error Classification
6.2.2.1. Correctable Errors
6.2.2.2. Uncorrectable Errors
6.2.2.2.1. Fatal Errors
6.2.2.2.2. Non-Fatal Errors
6.2.3. Error Signaling
6.2.3.1. Completion Status
6.2.3.2. Error Messages
6.2.3.2.1. Uncorrectable Error Severity Programming (Advanced Error Reporting)
6.2.3.2.2. Masking Individual Errors
6.2.3.2.3. Error Pollution
6.2.3.2.4. Advisory Non-Fatal Error Cases
6.2.3.2.4.1. Completer Sending a Completion with UR/CA Status
6.2.3.2.4.2. Intermediate Receiver
6.2.3.2.4.3. Ultimate PCI Express Receiver of a Poisoned TLP
6.2.3.2.4.4. Requester with Completion Timeout
6.2.3.2.4.5. Receiver of an Unexpected Completion
6.2.3.2.5. Requester Receiving a Completion with UR/CA Status
6.2.3.3. Error Forwarding (Data Poisoning)
6.2.3.4. Optional Error Checking
6.2.4. Error Logging
6.2.4.1. Root Complex Considerations (Advanced Error Reporting)
6.2.4.1.1. Error Source Identification
6.2.4.1.2. Interrupt Generation
6.2.4.2. Multiple Error Handling (Advanced Error Reporting Capability)
6.2.4.3. Advisory Non-Fatal Error Logging
6.2.4.4. TLP Prefix Logging
6.2.5. Sequence of Device Error Signaling and Logging Operations
6.2.6. Error Message Controls
6.2.7. Error Listing and Rules
6.2.7.1. Conventional PCI Mapping
6.2.8. Virtual PCI Bridge Error Handling
6.2.8.1. Error Message Forwarding and PCI Mapping for Bridge - Rules
6.2.9. Internal Errors
6.2.10. Downstream Port Containment (DPC)
6.2.10.1. DPC Interrupts
6.2.10.2. DPC ERR_COR Signaling
6.2.10.3. Root Port Programmed I/O (RP PIO) Error Controls
6.2.10.4. Software Triggering of DPC
6.2.10.5. DL_Active ERR_COR Signaling
6.3. Virtual Channel Support
6.3.1. Introduction and Scope
6.3.2. TC/VC Mapping and Example Usage
6.3.3. VC Arbitration
6.3.3.1. Traffic Flow and Switch Arbitration Model
6.3.3.2. VC Arbitration ( Arbitration Between VCs
6.3.3.2.1. Strict Priority Arbitration Model
6.3.3.2.2. Round Robin Arbitration Model
6.3.3.3. Port Arbitration ( Arbitration Within VC
6.3.3.4. Multi-Function Devices and Function Arbitration
6.3.4. Isochronous Support
6.3.4.1. Rules for Software Configuration
6.3.4.2. Rules for Requesters
6.3.4.3. Rules for Completers
6.3.4.4. Rules for Switches and Root Complexes
6.3.4.5. Rules for Multi-Function Devices
6.4. Device Synchronization
6.5. Locked Transactions
6.5.1. Introduction
6.5.2. Initiation and Propagation of Locked Transactions - Rules
6.5.3. Switches and Lock - Rules
6.5.4. PCI Express/PCI Bridges and Lock - Rules
6.5.5. Root Complex and Lock - Rules
6.5.6. Legacy Endpoints
6.5.7. PCI Express Endpoints
6.6. PCI Express Reset - Rules
6.6.1. Conventional Reset
6.6.2. Function-Level Reset (FLR)
6.7. PCI Express Hot-Plug Support
6.7.1. Elements of Hot-Plug
6.7.1.1. Indicators
6.7.1.1.1. Attention Indicator
6.7.1.1.2. Power Indicator
6.7.1.2. Manually-operated Retention Latch (MRL)
6.7.1.3. MRL Sensor
6.7.1.4. Electromechanical Interlock
6.7.1.5. Attention Button
6.7.1.6. Software User Interface
6.7.1.7. Slot Numbering
6.7.1.8. Power Controller
6.7.2. Registers Grouped by Hot-Plug Element Association
6.7.2.1. Attention Button Registers
6.7.2.2. Attention Indicator Registers
6.7.2.3. Power Indicator Registers
6.7.2.4. Power Controller Registers
6.7.2.5. Presence Detect Registers
6.7.2.6. MRL Sensor Registers
6.7.2.7. Electromechanical Interlock Registers
6.7.2.8. Command Completed Registers
6.7.2.9. Port Capabilities and Slot Information Registers
6.7.2.10. Hot-Plug Interrupt Control Register
6.7.3. PCI Express Hot-Plug Events
6.7.3.1. Slot Events
6.7.3.2. Command Completed Events
6.7.3.3. Data Link Layer State Changed Events
6.7.3.4. Software Notification of Hot-Plug Events
6.7.4. Firmware Support for Hot-Plug
6.7.5. Async Removal
6.8. Power Budgeting Capability
6.8.1. System Power Budgeting Process Recommendations
6.9. Slot Power Limit Control
6.10. Root Complex Topology Discovery
6.11. Link Speed Management
6.12. Access Control Services (ACS)
6.12.1. ACS Component Capability Requirements
6.12.1.1. ACS Downstream Ports
6.12.1.2. ACS Functions in Multi-Function Devices
6.12.1.3. Functions in Single-Function Devices
6.12.2. Interoperability
6.12.3. ACS Peer-to-Peer Control Interactions
6.12.4. ACS Violation Error Handling
6.12.5. ACS Redirection Impacts on Ordering Rules
6.12.5.1. Completions Passing Posted Requests
6.12.5.2. Requests Passing Posted Requests
6.13. Alternative Routing-ID Interpretation (ARI)
6.14. Multicast Operations
6.14.1. Multicast TLP Processing
6.14.2. Multicast Ordering
6.14.3. Multicast Capability Structure Field Updates
6.14.4. MC Blocked TLP Processing
6.14.5. MC_Overlay Mechanism
6.15. Atomic Operations (AtomicOps)
6.15.1. AtomicOp Use Models and Benefits
6.15.2. AtomicOp Transaction Protocol Summary
6.15.3. Root Complex Support for AtomicOps
6.15.3.1. Root Ports with AtomicOp Completer Capabilities
6.15.3.2. Root Ports with AtomicOp Routing Capability
6.15.3.3. RCs with AtomicOp Requester Capabilities
6.15.4. Switch Support for AtomicOps
6.16. Dynamic Power Allocation (DPA) Capability
6.16.1. DPA Capability with Multi-Function Devices
6.17. TLP Processing Hints (TPH)
6.17.1. Processing Hints
6.17.2. Steering Tags
6.17.3. ST Modes of Operation
6.17.4. TPH Capability
6.18. Latency Tolerance Reporting (LTR) Mechanism
6.19. Optimized Buffer Flush/Fill (OBFF) Mechanism
6.20. PASID TLP Prefix
6.20.1. Managing PASID TLP Prefix Usage
6.20.2. PASID TLP Layout
6.20.2.1. PASID field
6.20.2.2. Execute Requested
6.20.2.3. Privileged Mode Requested
6.21. Lightweight Notification (LN) Protocol
6.21.1. LN Protocol Operation
6.21.2. LN Registration Management
6.21.3. LN Ordering Considerations
6.21.4. LN Software Configuration
6.21.5. LN Protocol Summary
6.22. Precision Time Measurement (PTM) Mechanism
6.22.1. Introduction
6.22.2. PTM Link Protocol
6.22.3. Configuration and Operational Requirements
6.22.3.1. PTM Requester Role
6.22.3.2. PTM Responder Role
6.22.3.3. PTM Time Source Role -- Rules Specific to Switches
6.23. Readiness Notifications (RN)
6.23.1. Device Readiness Status (DRS)
6.23.2. Function Readiness Status (FRS)
6.23.3. FRS Queuing
7. Software Initialization and Configuration
7.1. Configuration Topology
7.2. PCI Express Configuration Mechanisms
7.2.1. PCI 3.0 Compatible Configuration Mechanism
7.2.2. PCI Express Enhanced Configuration Access Mechanism (ECAM)
7.2.2.1. Host Bridge Requirements
7.2.2.2. PCI Express Device Requirements
7.2.3. Root Complex Register Block
7.3. Configuration Transaction Rules
7.3.1. Device Number
7.3.2. Configuration Transaction Addressing
7.3.3. Configuration Request Routing Rules
7.3.4. PCI Special Cycles
7.4. Configuration Register Types
7.5. PCI-Compatible Configuration Registers
7.5.1. Type 0/1 Common Configuration Space
7.5.1.1. Command Register (Offset 04h)
7.5.1.2. Status Register (Offset 06h)
7.5.1.3. Cache Line Size Register (Offset 0Ch)
7.5.1.4. Latency Timer Register (Offset 0Dh)
7.5.1.5. Header Type Register (Offset 0Eh)
7.5.1.6. Interrupt Line Register (Offset 3Ch)
7.5.1.7. Interrupt Pin Register (Offset 3Dh)
7.5.1.8. Error Registers
7.5.2. Type 0 Configuration Space Header
7.5.2.1. Base Address Registers (Offset 10h - 24h)
7.5.2.2. Min_Gnt/Max_Lat Registers (Offset 3Eh/3Fh)
7.5.3. Type 1 Configuration Space Header
7.5.3.1. Base Address Registers (Offset 10h/14h)
7.5.3.2. Primary Bus Number (Offset 18h)
7.5.3.3. Secondary Latency Timer (Offset 1Bh)
7.5.3.4. Secondary Status Register (Offset 1Eh)
7.5.3.5. Prefetchable Memory Base/Limit (Offset 24h)
7.5.3.6. Bridge Control Register (Offset 3Eh)
7.6. PCI Power Management Capability Structure
7.7. MSI and MSI-X Capability Structures
7.7.1. Vector Control for MSI-X Table Entries
7.8. PCI Express Capability Structure
7.8.1. PCI Express Capability List Register (Offset 00h)
7.8.2. PCI Express Capabilities Register (Offset 02h)
7.8.3. Device Capabilities Register (Offset 04h)
7.8.4. Device Control Register (Offset 08h)
7.8.5. Device Status Register (Offset 0Ah)
7.8.6. Link Capabilities Register (Offset 0Ch)
7.8.7. Link Control Register (Offset 10h)
7.8.8. Link Status Register (Offset 12h)
7.8.9. Slot Capabilities Register (Offset 14h)
7.8.10. Slot Control Register (Offset 18h)
7.8.11. Slot Status Register (Offset 1Ah)
7.8.12. Root Control Register (Offset 1Ch)
7.8.13. Root Capabilities Register (Offset 1Eh)
7.8.14. Root Status Register (Offset 20h)
7.8.15. Device Capabilities 2 Register (Offset 24h)
7.8.16. Device Control 2 Register (Offset 28h)
7.8.17. Device Status 2 Register (Offset 2Ah)
7.8.18. Link Capabilities 2 Register (Offset 2Ch)
7.8.19. Link Control 2 Register (Offset 30h)
7.8.20. Link Status 2 Register (Offset 32h)
7.8.21. Slot Capabilities 2 Register (Offset 34h)
7.8.22. Slot Control 2 Register (Offset 38h)
7.8.23. Slot Status 2 Register (Offset 3Ah)
7.9. PCI Express Extended Capabilities
7.9.1. Extended Capabilities in Configuration Space
7.9.2. Extended Capabilities in the Root Complex Register Block
7.9.3. PCI Express Extended Capability Header
7.10. Advanced Error Reporting Capability
7.10.1. Advanced Error Reporting Extended Capability Header (Offset 00h)
7.10.2. Uncorrectable Error Status Register (Offset 04h)
7.10.3. Uncorrectable Error Mask Register (Offset 08h)
7.10.4. Uncorrectable Error Severity Register (Offset 0Ch)
7.10.5. Correctable Error Status Register (Offset 10h)
7.10.6. Correctable Error Mask Register (Offset 14h)
7.10.7. Advanced Error Capabilities and Control Register (Offset 18h)
7.10.8. Header Log Register (Offset 1Ch)
7.10.9. Root Error Command Register (Offset 2Ch)
7.10.10. Root Error Status Register (Offset 30h)
7.10.11. Error Source Identification Register (Offset 34h)
7.10.12. TLP Prefix Log Register (Offset 38h)
7.11. Virtual Channel Capability
7.11.1. Virtual Channel Extended Capability Header (Offset 00h)
7.11.2. Port VC Capability Register 1 (Offset 04h)
7.11.3. Port VC Capability Register 2 (Offset 08h)
7.11.4. Port VC Control Register (Offset 0Ch)
7.11.5. Port VC Status Register (Offset 0Eh)
7.11.6. VC Resource Capability Register
7.11.7. VC Resource Control Register
7.11.8. VC Resource Status Register
7.11.9. VC Arbitration Table
7.11.10. Port Arbitration Table
7.12. Device Serial Number Capability
7.12.1. Device Serial Number Extended Capability Header (Offset 00h)
7.12.2. Serial Number Register (Offset 04h)
7.13. PCI Express Root Complex Link Declaration Capability
7.13.1. Root Complex Link Declaration Extended Capability Header (Offset 00h)
7.13.2. Element Self Description (Offset 04h)
7.13.3. Link Entries
7.13.3.1. Link Description
7.13.3.2. Link Address
7.13.3.2.1. Link Address for Link Type 0
7.13.3.2.2. Link Address for Link Type 1
7.14. PCI Express Root Complex Internal Link Control Capability
7.14.1. Root Complex Internal Link Control Extended Capability Header (Offset 00h)
7.14.2. Root Complex Link Capabilities Register (Offset 04h)
7.14.3. Root Complex Link Control Register (Offset 08h)
7.14.4. Root Complex Link Status Register (Offset 0Ah)
7.15. Power Budgeting Capability
7.15.1. Power Budgeting Extended Capability Header (Offset 00h)
7.15.2. Data Select Register (Offset 04h)
7.15.3. Data Register (Offset 08h)
7.15.4. Power Budget Capability Register (Offset 0Ch)
7.16. ACS Extended Capability
7.16.1. ACS Extended Capability Header (Offset 00h)
7.16.2. ACS Capability Register (Offset 04h)
7.16.3. ACS Control Register (Offset 06h)
7.16.4. Egress Control Vector (Offset 08h)
7.17. PCI Express Root Complex Event Collector Endpoint Association Capability
7.17.1. Root Complex Event Collector Endpoint Association Extended Capability Header (Offset 00h)
7.17.2. Association Bitmap for Root Complex Integrated Endpoints (Offset 04h)
7.18. Multi-Function Virtual Channel Capability
7.18.1. MFVC Extended Capability Header (Offset 00h)
7.18.2. Port VC Capability Register 1 (Offset 04h)
7.18.3. Port VC Capability Register 2 (Offset 08h)
7.18.4. Port VC Control Register (Offset 0Ch)
7.18.5. Port VC Status Register (Offset 0Eh)
7.18.6. VC Resource Capability Register
7.18.7. VC Resource Control Register
7.18.8. VC Resource Status Register
7.18.9. VC Arbitration Table
7.18.10. Function Arbitration Table
7.19. Vendor-Specific Capability
7.19.1. Vendor-Specific Extended Capability Header (Offset 00h)
7.19.2. Vendor-Specific Header (Offset 04h)
7.20. RCRB Header Capability
7.20.1. RCRB Header Extended Capability Header (Offset 00h)
7.20.2. Vendor ID (Offset 04h) and Device ID (Offset 06h)
7.20.3. RCRB Capabilities (Offset 08h)
7.20.4. RCRB Control (Offset 0Ch)
7.21. Multicast Capability
7.21.1. Multicast Extended Capability Header (Offset 00h)
7.21.2. Multicast Capability Register (Offset 04h)
7.21.3. Multicast Control Register (Offset 06h)
7.21.4. MC_Base_Address Register (Offset 08h)
7.21.5. MC_Receive Register (Offset 10h)
7.21.6. MC_Block_All Register (Offset 18h)
7.21.7. MC_Block_Untranslated Register (Offset 20h)
7.21.8. MC_Overlay_BAR (Offset 28h)
7.22. Resizable BAR Capability
7.22.1. Resizable BAR Extended Capability Header (Offset 00h)
7.22.2. Resizable BAR Capability Register
7.22.3. Resizable BAR Control Register
7.23. ARI Capability
7.23.1. ARI Capability Header (Offset 00h)
7.23.2. ARI Capability Register (Offset 04h)
7.23.3. ARI Control Register (Offset 06h)
7.24. Dynamic Power Allocation (DPA) Capability
7.24.1. DPA Extended Capability Header (Offset 00h)
7.24.2. DPA Capability Register (Offset 04h)
7.24.3. DPA Latency Indicator Register (Offset 08h)
7.24.4. DPA Status Register (Offset 0Ch)
7.24.5. DPA Control Register (Offset 0Eh)
7.24.6. DPA Power Allocation Array
7.25. Latency Tolerance Reporting (LTR) Capability
7.25.1. LTR Extended Capability Header (Offset 00h)
7.25.2. Max Snoop Latency Register (Offset 04h)
7.25.3. Max No-Snoop Latency Register (Offset 06h)
7.26. TPH Requester Capability
7.26.1. TPH Requester Extended Capability Header (Offset 00h)
7.26.2. TPH Requester Capability Register (Offset 04h)
7.26.3. TPH Requester Control Register (Offset 08h)
7.26.4. TPH ST Table (Starting from Offset 0Ch)
7.27. Secondary PCI Express Extended Capability
7.27.1. Secondary PCI Express Extended Capability Header (Offset 00h)
7.27.2. Link Control 3 Register (Offset 04h)
7.27.3. Lane Error Status Register (Offset 08h)
7.27.4. Lane Equalization Control Register (Offset 0Ch)
7.27.5. Lane Equalization Control 2 Register (Offset TBD)
7.28. M-PCIe Extended Capability
7.28.1. M-PCIe Extended Capability Header (Offset 00h)
7.28.2. M-PCIe Capabilities Register (Offset 04h)
7.28.3. M-PCIe Control Register (Offset 08h)
7.28.4. M-PCIe Status Register (Offset 0Ch)
7.28.5. M-PCIe LANE Error Status Register (Offset 10h)
7.28.6. M-PCIe Phy Control Address Register (Offset 14h)
7.28.7. M-PCIe Phy Control Data Register (Offset 18h)
7.29. PASID Extended Capability Structure
7.29.1. PASID Extended Capability Header (Offset 00h)
7.29.2. PASID Capability Register (Offset 04h)
7.29.3. PASID Control Register (Offset 06h)
7.30. LNR Extended Capability
7.30.1. LNR Extended Capability Header (Offset 00h)
7.30.2. LNR Capability Register (Offset 04h)
7.30.3. LNR Control Register (Offset 04h)
7.31. DPC Extended Capability
7.31.1. DPC Extended Capability Header (Offset 00h)
7.31.2. DPC Capability Register (Offset 04h)
7.31.3. DPC Control Register (Offset 06h)
7.31.4. DPC Status Register (Offset 08h)
7.31.5. DPC Error Source ID Register (Offset 0Ah)
7.31.6. RP PIO Status Register (Offset 0Ch)
7.31.7. RP PIO Mask Register (Offset 10h)
7.31.8. RP PIO Severity Register (Offset 14h)
7.31.9. RP PIO SysError Register (Offset 18h)
7.31.10. RP PIO Exception Register (Offset 1Ch)
7.31.11. RP PIO Header Log Register (Offset 20h)
7.31.12. RP PIO ImpSpec Log Register (Offset 30h)
7.31.13. RP PIO TLP Prefix Log Register (Offset 34h)
7.32. Precision Time Management (PTM) Capability
7.32.1. PTM Extended Capability Header (Offset 00h)
7.32.2. PTM Capability Register (Offset 04h)
7.32.3. PTM Control Register (Offset 08h)
7.33. L1 PM Substates Extended Capability
7.33.1. L1 PM Substates Extended Capability Header (Offset 00h)
7.33.2. L1 PM Substates Capabilities Register (Offset 04h)
7.33.3. L1 PM Substates Control 1 Register (Offset 08h)
7.33.4. L1 PM Substates Control 2 Register (Offset 0Ch)
7.34. Function Readiness Status (FRS) Queuing Extended Capability
7.34.1. Function Readiness Status (FRS) Queuing Extended Capability Header (Offset 00h)
7.34.2. FRS Queuing Capability Register (Offset 04h)
7.34.3. FRS Queuing Status Register (Offset 08h)
7.34.4. FRS Queuing Control Register (Offset 0Ah)
7.34.5. FRS Message Queue Register (Offset 0Ch)
7.35. Readiness Time Reporting Extended Capability
7.35.1. Readiness Time Reporting Extended Capability Header (Offset 00h)
7.35.2. Readiness Time Reporting 1 (Offset 04h)
7.35.3. Readiness Time Reporting 2 (Offset 08h)
8. M-PCIe Logical Sub-Block
8.1. PHY Requirements
8.2. Configuration
8.2.1. Link Discovery and Configuration
8.2.2. Attributes
8.2.3. Remote Register Access Protocol (RRAP):
8.2.3.1. RRAP Timing Parameters
8.2.3.2. RRAP Address Maps
8.3. Symbol Encoding, Framing and Scrambling
8.3.1. 8b/10b Decode Rules
8.3.2. Framing and Application of Symbols to LANES
8.3.3. Data Scrambling
8.4. Link Initialization and Training
8.4.1. Training Sequence (TS) Ordered Sets
8.4.2. Electrical Idle
8.4.3. EIEOS for M-PCIe
8.4.4. Lane Polarity Inversion
8.4.5. Fast Training Sequence (FTS)
8.4.6. LINK Data RATE
8.4.7. LINK Width
8.4.8. LANE-to-LANE De-skew
8.4.9. LINK Training and Status State Machine (LTSSM)
8.4.9.1. Introduction
8.4.9.2. Detect
8.4.9.2.1. Detect.Quiet
8.4.9.2.2. Detect.Active
8.4.9.3. Configuration
8.4.9.3.1. Configuration.Start
8.4.9.3.2. Configuration.Software
8.4.9.3.3. Configuration.Update
8.4.9.3.4. Configuration.Confirm
8.4.9.3.5. Configuration.Complete
8.4.9.3.6. Configuration.Idle
8.4.9.3.7. Configuration.ExitToDetect
8.4.9.4. Recovery
8.4.9.4.1. Recovery.Entry
8.4.9.4.2. Recovery.ReConfig
8.4.9.4.3. Recovery.Complete
8.4.9.4.4. Recovery.Idle
8.4.9.4.5. Recovery.ExitToDetect
8.4.9.5. L0
8.4.9.6. L1
8.4.9.6.1. L1.Entry
8.4.9.6.2. L1.Idle
8.4.9.6.3. L1.Exit
8.4.9.7. L2
8.4.9.7.1. L2.Entry
8.4.9.7.2. L2.Idle
8.4.9.8. Disabled
8.4.9.9. Loopback
8.4.9.9.1. LoopbackMaster.Entry
8.4.9.9.2. LoopbackMaster.Active
8.4.9.9.3. LoopbackMaster.Exit
8.4.9.9.4. LoopbackSlave.Entry
8.4.9.9.5. LoopbackSlave.Active
8.4.9.9.6. LoopbackSlave.Exit
8.4.9.10. Hot Reset
8.4.10. Entry to HIBERN8
8.5. Receiver Error
8.6. Clock Tolerance Compensation
8.7. Dynamic LINK Bandwidth Management
8.7.1. LINK Rate Series and Speed Management
8.7.2. LINK Width Management
8.7.3. Dynamic LINK Re-Configuration
8.8. M-PHY Registers
8.8.1. M-PHY Capability Registers
8.8.2. M-PHY Configuration Attributes
9. Physical Layer Electrical Sub-Block Specification
9.1. Electrical Specification Organization
9.2. Interoperability Criteria
9.2.1. Data Rates
9.2.2. Refclk Architectures
9.3. Transmitter Specification
9.3.1. Measurement Setup for Characterizing Transmitters
9.3.1.1. Breakout and Replica Channels
9.3.2. Voltage Level Definitions
9.3.3. Tx Voltage Parameters
9.3.3.1. 2.5 and 5.0 GT/s Transmitter Equalization
9.3.3.2. 8.0 and 16.0 GT/s Transmitter Equalization
9.3.3.3. Tx Equalization Presets
9.3.3.4. Measuring Tx Equalization for 2.5 and 5.0G
9.3.3.5. Measuring Presets at 8.0 and 16.0GT/s
9.3.3.6. Preset Values
9.3.3.7. Method for Measuring VTX-DIFF-PP and VTX-DIFF-PP-LOW at 2.5 and 5.0 GT/s
9.3.3.8. Method for Measuring VTX-DIFF-PP and VTX-DIFF-PP-LOW at 8.0 and 16.0 GT/s
9.3.3.9. Coefficient Range and Tolerance
9.3.3.10. EIEOS and VTX-EIEOS-FS and VTX-EIEOS-RS Limits
9.3.3.11. Reduced Swing Signaling
9.3.3.12. Effective Tx Package Loss at 8.0G and 16G
9.3.4. Transmitter Margining
9.3.5. Tx Jitter Parameters
9.3.5.1. Post Processing Steps to Extract Jitter
9.3.5.2. De-embedding
9.3.5.3. Independent Refclk Measurement and Post Processing
9.3.5.4. Embedded and Non Embedded Refclk Measurement and Post Processing
9.3.5.5. Behavioral CDR Characteristics
9.3.5.6. Data Dependent and Uncorrelated Jitter
9.3.5.7. Data Dependent Jitter
9.3.5.8. Uncorrelated Total Jitter and Deterministic Jitter (TTX-UTJ and TTX-UDJDD)
9.3.5.9. Random Jitter (TTX-RJ)
9.3.5.10. Uncorrelated Total and Deterministic PWJ (TTX-UPW-TJ and TTX-UPW-DJDD)
9.3.5.11. Data Rate Dependent Parameters
9.3.6. Tx and Rx Return Loss
9.3.7. Transmitter PLL Bandwidth and Peaking
9.3.7.1. 2.5 GT/s and 5.0 GT/s Tx PLL Bandwidth and Peaking
9.3.7.2. 8.0 GT/s and 16.0 GT/s Tx PLL Bandwidth and Peaking
9.3.7.3. Series Capacitors
9.3.8. Data Rate Independent Tx Parameters
9.4. Receiver Specifications
9.4.1. Receiver Stressed Eye Specification
9.4.1.1. Breakout and Replica Channels
9.4.1.2. Calibration Channel Insertion Loss Characteristics
9.4.1.3. Post Processing Procedures
9.4.1.4. Behavioral Rx Package Models
9.4.1.5. Behavioral CDR Model
9.4.1.6. Behavioral Rx Equalization
9.4.1.7. No Behavioral Rx Equalization for 2.5 and 5.0 GT/s
9.4.1.8. Behavioral Rx Equalization for 8.0 and 16 GT/s
9.4.1.9. Behavioral CTLE (8.0 and 16 GT/s Only)
9.4.1.10. Behavioral DFE (8.0 and 16 GT/s Only)
9.4.2. Stressed Eye Test
9.4.2.1. Procedure for Calibrating a Stressed EH/EW Eye
9.4.2.2. Procedure for Testing Rx DUT
9.4.2.2.1. Sj Mask
9.4.2.3. Receiver Refclk Modes
9.4.2.3.1. Common Refclk Mode
9.4.2.3.2. Data Driven Mode
9.4.2.3.3. Independent Refclk Mode
9.4.3. Common receiver parameters
9.4.3.1. 5.0 GT/s Exit From Idle Detect (EFI)
9.4.3.2. Receiver Loopback
9.4.3.3. Receiver Return Loss
9.4.4. Low Frequency and Miscellaneous Signaling Requirements
9.4.4.1. ESD Standards
9.4.4.2. Channel AC Coupling Capacitors
9.4.4.3. Short Circuit Requirements
9.4.4.4. Transmitter and Receiver Termination
9.4.4.5. Electrical Idle
9.4.4.6. DC Common Mode Voltage
9.4.4.7. Receiver Detection
9.4.4.7.1. Differential Receiver Detect
9.5. Channel Tolerancing
9.5.1. Channel Compliance Testing
9.5.1.1. Behavioral Transmitter and Receiver Package Models
9.5.1.2. Simulation Tool Requirements
9.5.1.2.1. Simulation Tool Chain Inputs
9.5.1.2.2. Processing Steps
9.5.1.2.3. Simulation Tool Outputs
9.5.1.2.4. Open Source Simulation Tool
9.5.1.3. Behavioral Transmitter Parameters
9.5.1.3.1. Deriving Voltage and Jitter Parameters
9.5.1.4. Optimizing Tx/Rx Equalization (8.0 and 16G only)
9.5.1.5. Pass/Fail Eye Characteristics
9.5.1.6. Characterizing Channel Common Mode Noise
9.5.1.7. Verifying VCH-IDLE-DET-DIFFp-p
9.6. Refclk Specifications
9.6.1. Refclk Test Setup
9.6.2. Data Rate Independent Refclk Parameters
9.6.2.1. Low Frequency Refclk Jitter Limits
9.6.3. Refclk Architectures Supported
9.6.4. Filtering Functions Applied to Raw Data
9.6.4.1. PLL Filter Transfer Function Example
9.6.4.2. CDR Transfer Function Examples
9.6.5. Common Refclk Rx Architecture (CC)
9.6.5.1. Determining the Number of PLL BW and peaking Combinations
9.6.5.2. CDR and PLL BW and Peaking Limits for Common Refclk
9.6.6. Data Clocked Rx Architecture (DC)
9.6.6.1. PLL/CDR Peaking and BW Limits for DC Architecture
9.6.7. Independent Refclks (IR)
9.6.7.1. PLL/CDR Peaking and BW Limits for IR Architecture
9.6.7.1.1. Determining the Number of PLL BW/peaking combinations
9.6.8. Jitter Limits for Refclk Architectures
Appendixes
A. Isochronous Applications
A.1. Introduction
A.2. Isochronous Contract and Contract Parameters
A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot
A.2.2. Isochronous Payload Size
A.2.3. Isochronous Bandwidth Allocation
A.2.4. Isochronous Transaction Latency
A.2.5. An Example Illustrating Isochronous Parameters
A.3. Isochronous Transaction Rules
A.4. Transaction Ordering
A.5. Isochronous Data Coherency
A.6. Flow Control
A.7. Considerations for Bandwidth Allocation
A.7.1. Isochronous Bandwidth of PCI Express Links
A.7.2. Isochronous Bandwidth of Endpoints
A.7.3. Isochronous Bandwidth of Switches
A.7.4. Isochronous Bandwidth of Root Complex
A.8. Considerations for PCI Express Components
A.8.1. An Endpoint as a Requester
A.8.2. An Endpoint as a Completer
A.8.3. Switches
A.8.4. Root Complex
B. Symbol Encoding
C. Physical Layer Appendix
C.1. 8b/10b Data Scrambling Example
C.2. 128b/130b Data Scrambling Example
D. Request Dependencies
E. ID-Based Ordering Usage
E.1. Introduction
E.2. Potential Benefits with IDO Use
E.2.1. Benefits for MFD/RP Direct Connect
E.2.2. Benefits for Switched Environments
E.2.3. Benefits for Integrated Endpoints
E.2.4. IDO Use in Conjunction with RO
E.3. When to Use IDO
E.4. When Not to Use IDO
E.4.1. When Not to Use IDO with Endpoints
E.4.2. When Not to Use IDO with Root Ports
E.5. Software Control of IDO Use
E.5.1. Software Control of Endpoint IDO Use
E.5.2. Software Control of Root Port IDO Use
F. Message Code Usage
G. Protocol Multiplexing
G.1. Protocol Multiplexing Interactions with PCI Express
G.2. PMUX Packets
G.3. PMUX Packet Layout
G.3.1. PMUX Packet Layout for 8b10b Encoding
G.3.2. PMUX Packet Layout at 128b/130b Encoding
G.4. PMUX Control
G.5. PMUX Extended Capability
G.5.1. PCI Express Extended Header (Offset 00h)
G.5.2. PMUX Capability Register (Offset 04h)
G.5.3. PMUX Control Register (Offset 08h)
G.5.4. PMUX Status Register (Offset 0Ch)
G.5.5. PMUX Protocol Array (Offsets 10h Through 48h)
H. M-PCIe Timing Diagrams
H.1. Init to L0
H.2. L0 with Transmitter in STALL
H.3. L0 to L1
H.4. Downstream Port Initiated LINK Bandwidth Change
H.5. Upstream Port Initiated LINK Bandwidth Change
I. M-PCIe Compliance Patterns
I.1. RPAT
I.2. RPAT Variation by Lane
I.3. Continuous Mode CRPAT
I.4. Burst Mode CRPAT
Acknowledgements