دانلود کتاب Principles of VLSI RTL Design a Practical Guide

فهرست مطالب :

8.3.3 Interaction with Many Blocks......Page 5
8.4 Feedthrough......Page 7
Preface......Page 8
7.2 Disable Timing......Page 11
Cover......Page 1
8.3 RTL Characteristics......Page 2
8.3.2 Large Macros......Page 4
Foreword......Page 6
Acknowledgments......Page 9
7.3.1.2 Impact on Hold Analysis......Page 13
7.3.1.3 Protection Against Glitch Capture......Page 14
7.3.2.2 Impact on Hold Analysis......Page 16
1.1 A Brief Background......Page 17
7.4 Conclusion......Page 19
1.3 RTL Designs......Page 20
Index......Page 3
7.1.9 set_false_path -vs- set_clock_groups......Page 10
Contents......Page 12
7.3.2.1 Need for Multicycle --setup......Page 15
1.2 Hardware Description Languages (HDL)......Page 18
1.4 Design Goals and Constraints......Page 21
1.6.1 Simulation Friendly RTL......Page 24
1.6.2 Timing-Analysis Friendly RTL......Page 25
5.10.1 Internal Power Estimation......Page 26
5.10.4 Power Estimation at Non-gate Level......Page 27
5.11 Probabilistic Estimation......Page 28
1.6.3 Clock-Domain-Crossing (CDC ) Friendly RTL......Page 29
1.5 RTL Based Chip Design Flow......Page 22
1.6 Design Challenges......Page 23
5.12 Simulation Plus Probabilistic......Page 31
1.6.6 Timing-Exceptions Friendly RTL......Page 33
1.6.4 Power Friendly RTL......Page 30
1.6.5 DFT Friendly RTL......Page 32
1.6.7 Congestion Conscious RTL......Page 35
1.7 Summary......Page 36
2.1 Need for Unambiguous Simulation......Page 37
2.2.1.1 Combinational Read-Write Race......Page 38
2.2.1.2 Sequential Read-Write Race......Page 39
2.2.2 Write-Write Race......Page 40
Scenario 1......Page 42
2.2.4 Race Due to Inter-leaving of Assign with Procedural Block......Page 43
2.2.5 Avoiding Simulation Race......Page 44
2.3.1 Feedthroughs Because of Races......Page 45
2.3.2 Feedthroughs Without Simulation Race......Page 46
2.4 Simulation-Synthesis Mismatch......Page 48
2.5 Latch Inference......Page 50
2.6 Synchronous Reset......Page 52
2.7 Limitations of Simulation......Page 56
3.1 Scope of STA......Page 58
3.1.1 Simulation Limitations in the Context of Timing......Page 59
3.1.2 Exhaustiveness of STA......Page 60
3.2.2 Slew Parameters for Digital Logic......Page 62
3.2.3 Delay and Slew Measurement......Page 63
3.3.1.1 Gate's Geometry and Schematic......Page 64
3.3.1.2 Specific Path......Page 65
3.3.1.3 Specific Directions of the Transitions......Page 66
3.3.1.4 Conditions on Other Pins......Page 67
3.3.2.2 Input Slew......Page 68
3.3.2.3 Interpolation/Extrapolation......Page 69
3.3.2.6 Process......Page 71
3.3.2.8 Derating......Page 72
3.4.1 Pulse Width......Page 73
3.4.3 Hold......Page 74
3.4.5 Removal......Page 75
3.5.1 Understanding Setup......Page 76
3.5.2 Understanding Hold......Page 77
3.7 Basic Analysis......Page 78
3.8 Uncertainty......Page 81
3.9 STA Contrasted with Simulation......Page 82
3.9.3 Hold Violation in STA, Setup Violation in Simulation......Page 83
3.10 Accurate Timing Simulation......Page 84
3.11 Limitations of Static Timing Analysis......Page 85
3.13 Conclusion......Page 86
4.1 Clock Domain......Page 87
4.2.1 Understanding Metastability......Page 88
4.2.2 Problems Due to Metastability......Page 89
4.3.1 Double Flop Synchronizer......Page 90
4.3.2 Mean Time Between Failures (MTBF)......Page 91
4.3.3 Meta Hardened Flops......Page 92
4.4.3 Enable Synchronization Method......Page 93
4.4.4 Cost of Enable Synchronization......Page 94
4.5.1 Slow to Fast Crossing......Page 95
4.5.2 Fast to Slow Crossing......Page 96
4.6.1 FIFO Basics......Page 97
4.6.2 Full and Empty Generation......Page 98
4.6.3 FIFO Limitations......Page 99
4.8.1 Using STA......Page 101
4.8.3 Using Rule Checkers......Page 102
5.1.1 Increasing Device Density......Page 104
5.1.4 Green Concerns......Page 105
5.3.1 Switching Activity......Page 108
5.3.6 Device State......Page 109
5.4.1 Shifter Instead of Multipliers......Page 110
5.4.3 Avoid Comparison......Page 111
5.4.4 Clock Gating......Page 112
5.4.4.1 Pulse Clipping, Spurious Clocking......Page 114
5.4.4.2 Integrated Clock Gating Cell......Page 115
5.4.4.4 Gating Location......Page 117
5.5 Supply Voltage......Page 119
5.5.1 Simulation Limitation......Page 120
5.5.3 Implication on Backend......Page 121
5.6 Selective Shut Down......Page 122
5.6.1 Need for Isolation......Page 123
5.6.2 Generation of Power-Enable......Page 124
5.6.3 Power Sequencing......Page 125
5.10 Power Estimation......Page 126
5.10.1 Internal Power Estimation......Page 129
5.10.2 Switching Power Estimation......Page 130
5.11 Probabilistic Estimation......Page 131
5.11.1 Spatial Correlation......Page 132
5.11.2 Temporal Correlation......Page 134
5.13 CPF/UPF......Page 136
6.1.1 Manufacturing Defect -- Vis-a-Vis -- Design Defect......Page 138
6.1.3 Cost Considerations......Page 139
6.2.1 Controllability and Observability Conflict......Page 140
6.3.1 Need for Simultaneous Control......Page 141
6.3.2 Complexity Due to Signal Relationship......Page 142
6.3.3 Need for Many Control and Observe Points......Page 143
6.4.1 Scan Flop......Page 144
6.4.3 Timing Impact of Scan Flops......Page 145
6.4.4 Area Impact of Scan Flops......Page 146
6.5.2 Capture......Page 147
6.5.3 ShiftOut......Page 148
6.5.5 Chain Length......Page 149
6.6.2 Uncontrollable Flops......Page 150
6.6.2.1 Asynchronous Controls......Page 151
6.7.2 Scan Wrap......Page 152
6.8 Memory Testing......Page 153
6.10 Combinational Loops......Page 155
6.11 Power Impact......Page 156
6.13 Conclusion......Page 157
7.1 False Paths......Page 159
7.1.1 False Paths Due to Specific Protocol......Page 160
7.1.3 False Paths Due to CDC......Page 162
7.1.4 False Paths Due to Multi Mode......Page 163
7.1.5 False Paths Due to Pin Muxing......Page 164
7.1.6 False Paths Due to Exclusive Clocks......Page 166
7.1.7 False Paths Due to Asynchronous Control Signals......Page 167
7.1.8 False Paths Due to Quasi Static Signals......Page 168
7.2 Disable Timing......Page 169
7.3.1.1 Need for Multicycle -setup......Page 170
7.3.1.2 Impact on Hold Analysis......Page 171
7.3.1.3 Protection Against Glitch Capture......Page 172
7.3.2.1 Need for Multicycle --setup......Page 173
7.3.2.2 Impact on Hold Analysis......Page 174
7.3.2.3 Protection Against Data Loss......Page 175
7.3.5 Multicycle Paths for Deep Logic......Page 176
7.4 Conclusion......Page 177
8.1 Impact of Congestion......Page 179
8.3 RTL Characteristics......Page 180
8.3.1 High Utilization......Page 181
8.3.2 Large Macros......Page 182
8.3.2.1 Composite Macro......Page 183
8.3.3.1 Wide Fanout......Page 184
8.4 Feedthrough......Page 185
8.5 Conclusion......Page 186
Appendix A Interleaving of Processes......Page 187
Index......Page 189