دانلود کتاب VLSI for Neural Networks and Artificial Intelligence

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Front Matter....Pages i-x
Analog VLSI Neural Learning Circuits — A Tutorial....Pages 1-23
An Analog CMOS Implementation of a Kohonen Network with Learning Capability....Pages 25-34
Back-Propagation Learning Algorithms for Analog VLSI Implementation....Pages 35-44
An Analog Implementation of the Boltzmann Machine with Programmable Learning Algorithms....Pages 45-52
A VLSI Design of the Minimum Entropy Neuron....Pages 53-60
A Multi-Layer Analog VLSI Architecture for Texture Analysis Isomorphic to Cortical Cells in Mammalian Visual System....Pages 61-70
A VLSI Pipelined Neuroemulator....Pages 71-80
A Low Latency Digital Neural Network Architecture....Pages 81-91
MANTRA: A Multi-Model Neural-Network Computer....Pages 93-102
SPERT: A Neuro-Microprocessor....Pages 103-107
Design of Neural Self-Organization Chips for Semantic Applications....Pages 109-117
VLSI Implementation of a Digital Neural Network with Reward-Penalty Learning....Pages 119-127
Asynchronous VLSI Design for Neural System Implementation....Pages 129-139
VLSI-Implementation of Associative Memory Systems for Neural Information Processing....Pages 141-150
A Dataflow Approach for Neural Networks....Pages 151-158
A Custom Associative Chip Used as a Building Block for a Software Reconfigurable Multi-Network Simulator....Pages 159-166
Parallel Implementation of Neural Associative Memories on RISC Processors....Pages 167-176
Reconfigurable Logic Implementation of Memory-Based Neural Networks: A Case Study of the CMAC Network....Pages 177-186
A Cascadable VLSI Design for GENET....Pages 187-196
Parametrised Neural Network Design and Compilation into Hardware....Pages 197-206
Knowledge Processing in Neural Architecture....Pages 207-216
Two Methods for Solving Linear Equations Using Neural Networks....Pages 217-229
Hardware Support for Data Parallelism in Production Systems....Pages 231-242
SPACE: Symbolic Processing in Associative Computing Elements....Pages 243-252
PALM: A Logic Programming System on a Highly Parallel Architecture....Pages 253-263
A Distributed Parallel Associative Processor (DPAP) for the Execution of Logic Programs....Pages 265-273
Performance Analysis of a Parallel VLSI Architecture for Prolog....Pages 275-284
A Prolog VLSI System for Real Time Applications....Pages 285-295
An Extended WAM Based Architecture for OR-Parallel Prolog Execution....Pages 297-306
Architecture and VLSI Implementation of a Pegasus-II Prolog Processor....Pages 307-315
Back Matter....Pages 317-320