دانلود کتاب VLSI: Systems on a Chip: IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI’99) December 1–4, 1999, Lisboa, Portugal

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Front Matter....Pages i-xviii
Optimizing Mixer Noise Performance: a 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application....Pages 1-10
An Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication Devices....Pages 11-22
A Design of Operational Amplifiers for Sigma Delta Modulators using 0.35um CMOS Process....Pages 23-34
A Low Power CMOS Micromixer for GHz Wireless Applications....Pages 35-46
High Current, Low Voltage Current Mirrors and Applications....Pages 47-60
Nonlinearity Analysis of a Short Channel CMOS Circuit for RFIC Applications....Pages 61-68
A Fast Parametric Model for Contact-Substrate Coupling....Pages 69-76
A Feature Associative Processor for Image Recognition Based on a A-D Merged Architecture....Pages 77-88
Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications....Pages 89-100
Implementation of a Wavelet Transform Architecture for Image Processing....Pages 101-112
Scalable Run Time Reconfigurable Architecture....Pages 113-124
Frontier: A Fast Placement System for FPGAS....Pages 125-136
Dynamically Reconfigurable Implementation of Control Circuits....Pages 137-148
An IEEE Compliant Floating Point MAF....Pages 149-160
Design and Analysis of On-Chip CPU Pipelined Caches....Pages 161-172
Synchronous to Asynchronous Conversion....Pages 173-180
Clock Distribution Strategy for IP-based Development....Pages 181-191
An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures....Pages 192-205
Single Ended Pass-Transistor Logic....Pages 206-217
Multithreshold Voltage Technology for Low Power Bus Architecture....Pages 219-232
Integrating Dynamic Power Management in the Design Flow....Pages 233-244
Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI....Pages 245-256
On Defect Level Estimation and the Clustering Effect....Pages 257-268
FASTNR: An Efficient Fault Simulator for Linear and Nonlinear DC Circuits....Pages 269-280
Design Error Diagnosis in Digital Circuits without Error Model....Pages 281-292
Efficient RLC Macromodels for Digital IC Interconnect....Pages 293-304
A Decomposition-Based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications....Pages 305-317
A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements....Pages 318-325
RF Interface Design Using Mixed Mode Methodology....Pages 326-333
History-Based Dynamic Minimization During BDD Construction....Pages 334-345
AURA II: Combining Negative Thinking and Branch-and -Bound in Unate Covering Problems....Pages 346-361
Satisfiability-Based Functional Delay Fault Testing....Pages 362-372
Verification of Abstracted Instruction Cache of TITAC2: A Case Study....Pages 373-384
Speeding up Look-up-Table Driven Logic Simulation....Pages 385-397
Efficient Verification of Behavioral Models Using the Sequential Sampling Technique....Pages 398-406
Embedded Systems Design and Verification: Reuse Oriented Prototyping Methodologies....Pages 407-414
A Virtual CMOS Library Approach for Fast Layout Synthesis....Pages 415-426
RT-Level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime....Pages 427-438
Designing a Mask Programmable Matrix for Sequential Circuits....Pages 439-446
Placement Benchmarks for 3-D VLSI....Pages 447-455
Substrate Noise: Analysis, Models, and Optimization....Pages 456-472
Architectural Transformations for Hierarchical Algorithmic Descriptions....Pages 473-484
An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs....Pages 485-496
Object-Oriented Modeling and Co-Simulation of Embedded Systems....Pages 497-508
Architectural Synthesis with Interconnection Cost Control....Pages 509-520
CAE Environment for Electromechanical Microsystems....Pages 521-532
Cost Consideration for Application Specific Microsystems’ Physical Design Stages....Pages 533-542
Moving MEMS into Mainstream Applications: The MEMSCAP Solution....Pages 544-555
Trends in RF Simulation Algorithms....Pages 557-568
Device Modeling and Measurement for RF Systems....Pages 569-582
Reconfigurable Computing: Viable Applications and Trends....Pages 583-594
Hardware Synthesis from Term Rewriting Systems....Pages 595-619
A Synthesis Algorithm for Modular Design of Pipelined Circuits....Pages 620-635
A Methodology and Associated CAD Tools for Support of Concurrent Design of MEMS....Pages 636-648
SIPPs, Why Do We Need a New Standard for Interconnect Process Parameters ?....Pages 649-658
ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect....Pages 659-670
Back Matter....Pages 671-675